| BlueNRG-1 network coprocessor (SPI mode)

SPI protocol specification

This document outlines the main specification for the SPI protocol to be used in the BlueNRG-1 network coprocessor configuration.
ST has already a family of product (BlueNRG and BlueNRG-MS) implementing the SPI protocol with hardware support.
The specification aims at achieving the following targets:

- Very similar to BlueNRG, BlueNRG-MS protocol
- Power efficient
- Code efficient
- Fast data transfer

# STEVAL-IDB007V1 SPI protocol HW, SW configuration

- In order to use the STEVAL-IDB007V1 for the BlueNRG-1 SPI network coprocessor configuration, the following hardware changes must be done:
  - Make a short at positions R59, R60, R61, R62 on STEVAL-IDB007V1 platform (refer to STEVAL-IDB007V1 schematics).
- In order to use the BlueNRG-1 GUI in SPI mode, with the STEVAL-IDB007V1 modified for the BlueNRG-1 network coprocessor configuration, the following steps must be followed:
  - Update the BlueNRG-1 firmware to the latest version of DTM (DTM_SPI.hex available on BlueNRG-1 DK SW package, folder: Firmware/BLE_Examples/DTM) by using the BlueNRG-1 Flasher PC utility.
  - Open the BlueNRG GUI 2.2.2 version or later

# SPI protocol hardware details

- The SPI port requires five pins:
  - SPI clock
  - SPI MOSI
  - SPI MISO
  - SPI CS
  - SPI IRQ

- The maximum SPI baud rate supported is 1MHz. The timing diagram adopted is CPOL 0 and CPHA 1, which means data are captured on the SPI clock's falling edge and data is output on a rising edge. The SPI CS acts also as wake up pin for the BlueNRG-1, so that if the SPI CS pin is low (external uC select the BlueNRG-1 for communication) the BlueNRG-1 is woken up if it was asleep.The BlueNRG-1 notifies event pending to the external uC through the SPI IRQ pin. If the SPI IRQ pin is high, the BlueNRG-1 has at least an event for the external uC.

Table 1: BlueNRG-1 SPI lines

# SPI communication protocol

- To communicate with the BlueNRG-1, the data on the SPI bus must be formatted as described in this section. An SPI transaction is defined from a falling edge of the SPI CS signal to the next rising edge of the SPI CS signal. Each SPI transaction must contain only one data frame. Each data frame should contain at least 5 bytes of header, and may have from 0 to N bytes of data.

## Generic transaction

Figure 1: Generic SPI transaction

- Figure 1 shows a generic SPI transaction, the list of steps is as follow:
  1. The external uC lowers the SPI CS signal to start the communication
  2. The BlueNRG-1 raises the SPI IRQ signal to indicate that it is ready for the communication. The time t1 change according to the state of the BlueNRG-1. This time t1 can include wake up of the BlueNRG-1 and preparation of the header part of the frame.
  3. The external uC must wait for the SPI IRQ signal to become high and then start to transfer the five bytes of the header that include the control field with the intended operation.In addition, the external uC read five bytes from the BlueNRG-1, which includes information about the actual size of the read buffer and of the write buffer.
  4. The external uC, after checking the 5 bytes of header, will perform data transaction.
  5. The BlueNRG-1 will lower SPI IRQ signal after the five bytes header are transferred.
  6. The external uC waits the SPI IRQ is low before raise the SPI CS signal to mark the end of the communication.
- Some important notes are:
  - Setting the SPI CS signal low will wake up BlueNRG-1 if the device is asleep.
  - If the SPI IRQ signal is low before setting the SPI CS signal low, this means the BlueNRG-1 has no data events for the external uC, so the read buffer size is zero (RBUF=0).
  - The time t1 is the time between wake-up (point a in Figure 1) and the BlueNRG-1 being ready to perform the SPI transaction (point b in Figure 1). The time t1 ranges is from minimal value (the BlueNRG-1 already awake when the SPI CS is asserted), to a maximum value that involves wake-up sequence and software boot.
  - Even if there are events pending after the completion of the transaction, the SPI IRQ signal will go low to allow the BlueNRG-1 updating the five bytes header an rearming the SPI for next transaction (after this delay the SPI IRQ signal will go high again if events are pending).
  - The SPI CS signal marks the begin and end of the transaction
  - The SPI CS high marks the end of the transaction and must be set to high only when IRQ line is low.
  - The gap between the header and the data is not mandatory, but it is normally required by the external uC to process the header and check if there is enough space in the buffers to perform the wanted transaction.
  - When the SPI IRQ signal is high, the five bytes header are locked and cannot be modified by BlueNRG-1 firmware.

## Header

Figure 2: SPI header format

- The header of the external uC (the SPI master) is on the MOSI line, which is composed by one control byte (CTRL) and four bytes 0x00. CTRL field can have only the value of 0x0A (SPI write) or 0x0B (SPI read). The BlueNRG-1 returns the header on the MISO line at the same time. When the BlueNRG-1 asserts the SPI IRQ signal, it is ready. Otherwise, the BlueNRG-1 is still not initialized. External uC must wait for the IRQ line to become high and perform a five bytes transaction. The 5 bytes in the MISO line gives one byte of starting frame, two bytes with the size of the write buffer (WBUF) and two bytes with the size of the read buffer (RBUF). The endianness for WBUF and RBUF is LSB first. The value in WBUF means how many bytes the master can write to the BlueNRG-1. The value in RBUF means how many bytes in the BlueNRG-1 are waiting to be read by the external uC.

## Read transaction

- A read transaction is performed when the BlueNRG-1 raises the SPI IRQ line before the SPI CS signal is lowered by the external uC.

Figure 3: SPI Read transaction

- In this case, the SPI IRQ signal is high indicating the BlueNRG-1 is awake and ready to perform the SPI transaction, after a hardware dependent setup time t2, typical value is 1.5 us. The transaction will be performed as follow:
  1. An event has been generated by the BlueNRG-1 (point a in Figure 3)
  2. The external uC lower the SPI CS signal to initiate a transaction (point b in Figure 3)
  3. Since the SPI IRQ signal is high, the external uC initiate a data transfer after t2. The external uC will transfer five bytes as follow [0x0B, XX, XX, XX, XX]. The WBUF and RBUF sizes are read from the SPI MISO signal.
  4. The external uC will perform the read data transaction for RBUF bytes. (Note: if RBUF is 0, this is an unexpected condition since the BlueNRG-1 is indicating that data is available, in any case the transaction needs to be completed by reading no bytes).
  5. The BlueNRG-1 will lower SPI IRQ signal after the five bytes header are transferred.
  6. The external uC will raise the SPI CS signal to mark the end of the transaction.

## Write transaction

- A write transaction is performed by the external uC to send a command to the BlueNRG-1. The BlueNRG-1 can be awake or sleeping when the SPI CS signal is lowered by the external uC. The assertion of the SPI CS signal will wakeup the BlueNRG-1, if asleep.

Figure 4: SPI Write transaction

- The transaction will be performed as follow:
  1. The external uC lower the SPI CS signal to initiate a transaction.
  2. The BlueNRG-1 raises the SPI IRQ signal to indicate that is ready with t1 >= 0.
  3. The external uC waits for SPI IRQ signal to become high and start a transfer of five bytes sending the code of the intended operation and reading the read buffer and write buffer size. The external uC will transfer five bytes as follow [0x0A, XX, XX, XX, XX]. The WBUF and RBUF values are sampled in the SPI MISO signal.
  4. The BlueNRG-1 will lower the SPI IRQ after the five bytes header are transferred.
  5. The external uC checks whether the WBUF allow sending the command. If yes, it will perform the data transaction, otherwise the external uC must waits.
  6. The external uC will wait for the SPI IRQ signal to be low before close the communication.
  7. The external uC will raise the SPI CS to mark the end of the transaction.

## Error transaction

- This section list the BlueNRG-1 firmware behavior when some error transactions are performed:
  - Incomplete header transaction (0 to 4): the BlueNRG-1 ignores the transaction.
  - The external uC does not wait for the SPI IRQ signal low before raising the SPI CS signal: the BlueNRG-1 will low the SPI IRQ signal when the SPI CS signal is high.
  - The external uC does not wait for the SPI IRQ signal high before starting SPI clock: the result is acquisition of corrupted data both master and slave side.
  - Incomplete read transaction: the master loses the event.
  - Incomplete write transaction: the BlueNRG-1 will store the bytes written by the external uC. During next write operation the BlueNRG-1 will get the new bytes trying to get a complete frame according Bluetooth protocol.

  - Two commands in a row without reading event for command: the BlueNRG-1 will parse the two commands and then it will generate the corresponding events.

## SPI state machine

- Here after the description of the BlueNRG-1 SPI state machine.

Table 2: BlueNRG-1 SPI state machine states

Figure 5: SPI protocol state machine

## External uC behavior

- The external uC must act as follows according to the information from the BlueNRG-1:
  - SPI IRQ signal
  - information from header frame WBUF and RBUF.

Table 3: BlueNRG-1 SPI inputs

Figure 6: Expected uC SPI protocol state machine

## Waveform acquisition

Figure 7: HCI_READ_LOCAL_VERSION_INFORMATION SPI waveform

Figure 8: HCI_READ_LOCAL_VERSION_INFORMATION SPI waveform zoom

Figure 9: HCI_COMMAND_COMPLETE_EVENT SPI waveform