| BlueNRG-1 Peripherals drivers APIs

- Main Page
- Modules
- Classes
- Files

- File List
- File Members

BlueNRG1_spi.h
Go to the documentation of this file.
1
23 /* Define to prevent recursive inclusion -------------------------------------*/
24 #ifndef BLUENRG1_SPI_H
25 #define BLUENRG1_SPI_H
26
27 #ifdef __cplusplus
28 extern "C" {
29 #endif
30
31 /* Includes ------------------------------------------------------------------*/
32 #include "BlueNRG1.h"
33
49 typedef struct {
50 uint8_t SPI_Mode;
53 uint8_t SPI_DataSize;
56 uint8_t SPI_CPOL;
59 uint8_t SPI_CPHA;
62 uint32_t SPI_BaudRate;
66 } SPI_InitType;
67
68
83 /* This macro checks if SPI baud rate is a valid value */
84 #define IS_SPI_BAUDRATE(BAUDRATE) ((BAUDRATE>=10000) && (BAUDRATE<=8000000))
85
93 #define SPI_FULL_DUPLEX_MODE ((uint32_t)0x00000000)
94 #define SPI_TRANSMIT_MODE ((uint32_t)0x00000001)
95 #define SPI_RECEIVE_MODE ((uint32_t)0x00000002)
96 #define SPI_COMBINED_MODE ((uint32_t)0x00000003)
97
98
99 #define IS_SPI_COM_MODE(MODE) (((MODE) == SPI_FULL_DUPLEX_MODE) || \
100 ((MODE) == SPI_TRANSMIT_MODE) || \
101 ((MODE) == SPI_RECEIVE_MODE) || \
102 ((MODE) == SPI_COMBINED_MODE))
103
113 #define SPI_Mode_Master ((uint8_t)0x00)
114 #define SPI_Mode_Slave ((uint8_t)0x01)
116 /* This macro checks if MODE is a valid SPI mode */
117 #define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \
118 ((MODE) == SPI_Mode_Slave))
119
128 #define SPI_DataSize_32b ((uint8_t)0x1F)
129 #define SPI_DataSize_31b ((uint8_t)0x1E)
130 #define SPI_DataSize_30b ((uint8_t)0x1D)
131 #define SPI_DataSize_29b ((uint8_t)0x1C)
132 #define SPI_DataSize_28b ((uint8_t)0x1B)
133 #define SPI_DataSize_27b ((uint8_t)0x1A)
134 #define SPI_DataSize_26b ((uint8_t)0x19)
135 #define SPI_DataSize_25b ((uint8_t)0x18)
136 #define SPI_DataSize_24b ((uint8_t)0x17)
137 #define SPI_DataSize_23b ((uint8_t)0x16)
138 #define SPI_DataSize_22b ((uint8_t)0x15)
139 #define SPI_DataSize_21b ((uint8_t)0x14)
140 #define SPI_DataSize_20b ((uint8_t)0x13)
141 #define SPI_DataSize_19b ((uint8_t)0x12)
142 #define SPI_DataSize_18b ((uint8_t)0x11)
143 #define SPI_DataSize_17b ((uint8_t)0x10)
144 #define SPI_DataSize_16b ((uint8_t)0x0F)
145 #define SPI_DataSize_15b ((uint8_t)0x0E)
146 #define SPI_DataSize_14b ((uint8_t)0x0D)
147 #define SPI_DataSize_13b ((uint8_t)0x0C)
148 #define SPI_DataSize_12b ((uint8_t)0x0B)
149 #define SPI_DataSize_11b ((uint8_t)0x0A)
150 #define SPI_DataSize_10b ((uint8_t)0x09)
151 #define SPI_DataSize_9b ((uint8_t)0x08)
152 #define SPI_DataSize_8b ((uint8_t)0x07)
153 #define SPI_DataSize_7b ((uint8_t)0x06)
154 #define SPI_DataSize_6b ((uint8_t)0x05)
155 #define SPI_DataSize_5b ((uint8_t)0x04)
156 #define SPI_DataSize_4b ((uint8_t)0x03)
158 /* This macro checks if DATASIZE is a valid SPI data size value */
159 #define IS_SPI_DATASIZE(DATASIZE) ((DATASIZE > 2) && (DATASIZE < 0x20))
160
169 #define SPI_CPOL_Low ((uint8_t)0)
170 #define SPI_CPOL_High ((uint8_t)1)
172 /* This macro checks if CPOL is a valid clock polarity value */
173 #define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \
174 ((CPOL) == SPI_CPOL_High))
175
176
185 #define SPI_CPHA_1Edge ((uint8_t)0)
186 #define SPI_CPHA_2Edge ((uint8_t)1)
188 /* This macro checks if CPHA is a valid clock phase value */
189 #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \
190 ((CPHA) == SPI_CPHA_2Edge))
191
199 #define SPI_IT_TE ((uint8_t)0x20)
200 #define SPI_IT_TUR ((uint8_t)0x10)
201 #define SPI_IT_TX ((uint8_t)0x08)
202 #define SPI_IT_RX ((uint8_t)0x04)
203 #define SPI_IT_RT ((uint8_t)0x02)
204 #define SPI_IT_ROR ((uint8_t)0x01)
205 #define SPI_IT_MSK ((uint8_t)0x3F)
207 /* This macro checks if IT is a valid combination of interrupt */
208 #define IS_SPI_CONFIG_IT(IT) (((IT & ~SPI_IT_MSK) == 0x00) && ((IT) != 0x00))
209
210
211 /* This macro checks if IT is a valid clearable interrupt */
212 #define IS_SPI_CLEAR_IT(IT) (((IT) == SPI_IT_TUR) || \
213 ((IT) == SPI_IT_RT) || ((IT) == SPI_IT_ROR))
214
215 /* This macro checks if IT is a valid interrupt */
216 #define IS_SPI_GET_IT(IT) (((IT) == SPI_IT_TX) || ((IT) == SPI_IT_RX) || \
217 ((IT) == SPI_IT_RT) || ((IT) == SPI_IT_ROR) || \
218 ((IT) == SPI_IT_TUR) || ((IT) == SPI_IT_TE))
219
220
228 #define SPI_FLAG_TFE ((uint8_t)0x01)
229 #define SPI_FLAG_TNF ((uint8_t)0x02)
230 #define SPI_FLAG_RNE ((uint8_t)0x04)
231 #define SPI_FLAG_RFF ((uint8_t)0x08)
232 #define SPI_FLAG_BSY ((uint8_t)0x10)
234 /* This macro checks if FLAG is a valid flag */
235 #define IS_SPI_GET_FLAG(FLAG) (((FLAG) == SPI_FLAG_TFE) || ((FLAG) == SPI_FLAG_TNF) || \
236 ((FLAG) == SPI_FLAG_RNE) || ((FLAG) == SPI_FLAG_RFF) || \
237 ((FLAG) == SPI_FLAG_BSY))
238
246 #define SPI_DMAReq_Tx ((uint8_t)0x04)
247 #define SPI_DMAReq_Rx ((uint8_t)0x01)
249 /* This macro checks if DMAREQ is a valid DMA request */
250 #define IS_SPI_DMAREQ(DMAREQ) ((DMAREQ==SPI_DMAReq_Tx) || (DMAREQ==SPI_DMAReq_Rx) || (DMAREQ==(SPI_DMAReq_Rx | SPI_DMAReq_Tx)))
251
261 #define SPI_FIFO_LEV_1 ((uint8_t)0)
262 #define SPI_FIFO_LEV_4 ((uint8_t)1)
263 #define SPI_FIFO_LEV_8 ((uint8_t)2)
265 /* This macro checks if IS_SPI_FIFO_LEV is a valid FIFO level */
266 #define IS_SPI_FIFO_LEV(FIFO_LEV) ( ((FIFO_LEV) == SPI_FIFO_LEV_1) || \
267 ((FIFO_LEV) == SPI_FIFO_LEV_4) || \
268 ((FIFO_LEV) == SPI_FIFO_LEV_8))
269
279 #define SPI_ENDIAN_MSByte_MSBit ((uint8_t)0)
280 #define SPI_ENDIAN_LSByte_MSBit ((uint8_t)1)
281 #define SPI_ENDIAN_MSByte_LSBit ((uint8_t)2)
282 #define SPI_ENDIAN_LSByte_LSBit ((uint8_t)3)
285 #define IS_SPI_ENDIAN(FORMAT) ( ((FORMAT) == SPI_ENDIAN_MSByte_MSBit) || \
286 ((FORMAT) == SPI_ENDIAN_LSByte_MSBit) || \
287 ((FORMAT) == SPI_ENDIAN_MSByte_LSBit) || \
288 ((FORMAT) == SPI_ENDIAN_LSByte_LSBit))
289
297 /* This macro checks if IS_WAIT_VALUE is a valid value */
298 #define IS_WAIT_VALUE(VALUE) ( (VALUE) < 16)
299
320 /* SPI initialization and configuration */
321 void SPI_StructInit(SPI_InitType* SPI_InitStruct);
322 void SPI_DeInit(void);
323 void SPI_Init(SPI_InitType* SPI_InitStruct);
324 void SPI_Cmd(FunctionalState NewState);
325 void SPI_ITConfig(uint8_t SPI_IT, FunctionalState NewState);
326 void SPI_DataSizeConfig(uint16_t SPI_DataSize);
327
328 /* SPI data register access */
329 void SPI_SendData(uint32_t Data);
330 uint32_t SPI_ReceiveData(void);
331
332 /* Interrupt and status management */
333 FlagStatus SPI_GetFlagStatus(uint16_t SPI_FLAG);
334 ITStatus SPI_GetITStatus(uint8_t SPI_IT);
335 void SPI_ClearITPendingBit(uint8_t SPI_IT);
336
337 /* Clear RX and TX FIFO */
338 void SPI_ClearRXFIFO(void);
339 void SPI_ClearTXFIFO(void);
340
341 /* Communication mode configuration in SPI master mode */
342 void SPI_SetMasterCommunicationMode(uint32_t Mode);
343 void SPI_SetDummyCharacter(uint32_t NullCharacter);
344 void SPI_SetNumFramesToReceive(uint16_t Number);
345 void SPI_SetNumFramesToTransmit(uint16_t Number);
346 void SPI_SlaveSwSelection(FunctionalState NewState);
347 void SPI_EndianFormatReception(uint8_t Endian);
348 void SPI_EndianFormatTransmission(uint8_t Endian);
349 void SPI_DelayBetweenFrames(uint8_t Delay);
350 void SPI_DelayDataInput(FunctionalState NewState);
351
352 /* Special functionality */
353 void SPI_SlaveModeOutputCmd(FunctionalState NewState);
354
355 /* DMA channel control */
356 void SPI_DMACmd(uint8_t SPI_DMAReq, FunctionalState NewState);
357
358 /* SPI FIFO interrupt level */
359 void SPI_TxFifoInterruptLevelConfig(uint8_t SPI_TX_FIFO_LEV);
360 void SPI_RxFifoInterruptLevelConfig(uint8_t SPI_RX_FIFO_LEV);
361
374 #ifdef __cplusplus
375 }
376 #endif
377
378 #endif /*BLUENRG1_SPI_H */
379
380 /******************* (C) COPYRIGHT 2016 STMicroelectronics *****END OF FILE****/
SPI_SetNumFramesToReceive
void SPI_SetNumFramesToReceive(uint16_t Number)
Set the number of frames to receive from slave.
Definition: BlueNRG1_spi.c:467
SPI_Cmd
void SPI_Cmd(FunctionalState NewState)
Enables or disables the SPI peripheral.
Definition: BlueNRG1_spi.c:206
SPI_GetITStatus
ITStatus SPI_GetITStatus(uint8_t SPI_IT)
Checks whether the specified SPI interrupt has occurred or not.
Definition: BlueNRG1_spi.c:357
SPI_DMACmd
void SPI_DMACmd(uint8_t SPI_DMAReq, FunctionalState NewState)
Enables or disables the SPI DMA interface.
Definition: BlueNRG1_spi.c:620
SPI_SendData
void SPI_SendData(uint32_t Data)
Transmits a Data through the SPI peripheral.
Definition: BlueNRG1_spi.c:278
SPI_DeInit
void SPI_DeInit(void)
Deinitializes the SPI peripheral registers to their default reset values.
Definition: BlueNRG1_spi.c:132
SPI_SetNumFramesToTransmit
void SPI_SetNumFramesToTransmit(uint16_t Number)
Set the number of frames to transmit to slave.
Definition: BlueNRG1_spi.c:478
SPI_SlaveSwSelection
void SPI_SlaveSwSelection(FunctionalState NewState)
Master can select the slave by driving the CS pin by software.
Definition: BlueNRG1_spi.c:491
SPI_SetDummyCharacter
void SPI_SetDummyCharacter(uint32_t NullCharacter)
Set the dummy character used for the SPI master communication.
Definition: BlueNRG1_spi.c:456
SPI_ITConfig
void SPI_ITConfig(uint8_t SPI_IT, FunctionalState NewState)
Enables or disables the specified SPI interrupts.
Definition: BlueNRG1_spi.c:235
SPI_DataSizeConfig
void SPI_DataSizeConfig(uint16_t SPI_DataSize)
Configures the data size for the selected SPI.
Definition: BlueNRG1_spi.c:305
SPI_InitType
Structure definition of SPI initialization.
Definition: BlueNRG1_spi.h:49
SPI_InitType::SPI_Mode
uint8_t SPI_Mode
Definition: BlueNRG1_spi.h:50
SPI_InitType::SPI_CPHA
uint8_t SPI_CPHA
Definition: BlueNRG1_spi.h:59
SPI_ClearTXFIFO
void SPI_ClearTXFIFO(void)
Clear all data present within the TX FIFO of the SPI peripherial. SPI peripherial clocks have to be e...
Definition: BlueNRG1_spi.c:415
SPI_ClearRXFIFO
void SPI_ClearRXFIFO(void)
Clear all data present within the RX FIFO of the SPI peripherial. SPI peripherial clocks have to be e...
Definition: BlueNRG1_spi.c:401
SPI_GetFlagStatus
FlagStatus SPI_GetFlagStatus(uint16_t SPI_FLAG)
Checks whether the specified SPI flag is set or not.
Definition: BlueNRG1_spi.c:327
SPI_ClearITPendingBit
void SPI_ClearITPendingBit(uint8_t SPI_IT)
Clears the SPI interrupt pending bits.
Definition: BlueNRG1_spi.c:386
SPI_InitType::SPI_CPOL
uint8_t SPI_CPOL
Definition: BlueNRG1_spi.h:56
SPI_TxFifoInterruptLevelConfig
void SPI_TxFifoInterruptLevelConfig(uint8_t SPI_TX_FIFO_LEV)
Sets the SPI interrupt FIFO level.
Definition: BlueNRG1_spi.c:584
SPI_InitType::SPI_DataSize
uint8_t SPI_DataSize
Definition: BlueNRG1_spi.h:53
SPI_ReceiveData
uint32_t SPI_ReceiveData(void)
Returns the most recent received data by the SPI peripheral.
Definition: BlueNRG1_spi.c:289
SPI_InitType::SPI_BaudRate
uint32_t SPI_BaudRate
Definition: BlueNRG1_spi.h:62
SPI_DelayBetweenFrames
void SPI_DelayBetweenFrames(uint8_t Delay)
Configure the delay between the frames. The MSPIWAIT value is used to insert a wait state between fra...
Definition: BlueNRG1_spi.c:544
SPI_StructInit
void SPI_StructInit(SPI_InitType *SPI_InitStruct)
Fills each SPI_InitStruct member with its default value.
Definition: BlueNRG1_spi.c:182
SPI_SlaveModeOutputCmd
void SPI_SlaveModeOutputCmd(FunctionalState NewState)
Enables or disables the output if in slave mode.
Definition: BlueNRG1_spi.c:258
SPI_DelayDataInput
void SPI_DelayDataInput(FunctionalState NewState)
Master insert a delay of two clock cycle if enabled.
Definition: BlueNRG1_spi.c:559
SPI_RxFifoInterruptLevelConfig
void SPI_RxFifoInterruptLevelConfig(uint8_t SPI_RX_FIFO_LEV)
Sets the SPI interrupt FIFO level.
Definition: BlueNRG1_spi.c:602
SPI_EndianFormatReception
void SPI_EndianFormatReception(uint8_t Endian)
Master can select the slave by driving the CS pin by software.
Definition: BlueNRG1_spi.c:511
SPI_EndianFormatTransmission
void SPI_EndianFormatTransmission(uint8_t Endian)
Master can select the slave by driving the CS pin by software.
Definition: BlueNRG1_spi.c:524
SPI_Init
void SPI_Init(SPI_InitType *SPI_InitStruct)
Initializes the SPI peripheral according to the specified parameters in the SPI_InitStruct.
Definition: BlueNRG1_spi.c:152
SPI_SetMasterCommunicationMode
void SPI_SetMasterCommunicationMode(uint32_t Mode)
Set the SPI communication mode.
Definition: BlueNRG1_spi.c:442