| BlueNRG-1 Peripherals drivers APIs

- Main Page
- Modules
- Classes
- Files

- File List
- File Members

BlueNRG1_spi.c
Go to the documentation of this file.
1
22 /* Includes ------------------------------------------------------------------*/
23 #include "BlueNRG1_spi.h"
24
45 #define MAX_SCR (255)
46 #define MAX_CPSVDR (254)
47 #define MIN_DIVIDER (1)
48 #define MAX_DIVIDER (65024) // MAX_CPSVDR * (MAX_SCR+1)
49
50 #define SPI_CLOCK (16000000)
51
90 void SPI_SetBaudrate(uint32_t Baudrate)
91 {
92 uint32_t c;
93 uint8_t scr = 1;
94 uint8_t cpsr = 2;
95
96 /* Check the parameters */
97 assert_param(IS_SPI_BAUDRATE(Baudrate));
98
99 /* bit rate is: 16MHz / (CPSDVR * (1+SCR))
100 and CPSDVR must be an even number from 2-254.
101 We calculate (1/2 * CPSDVR) * (1+SCR) */
102 c = SPI_CLOCK / (2 * Baudrate);
103
104 /* if the bit rate is possible */
105 if ((c >= MIN_DIVIDER) && (c <= MAX_DIVIDER)) {
106 /* adjust the ratio CPSDVR / (SCR+1) */
107 while (c > MAX_SCR) {
108 cpsr <<= 1;
109 c >>= 1;
110 }
111 scr = c - 1;
112 }
113 /* set dividers */
114 SPI->CPSR = cpsr;
115 SPI->CR0_b.SCR = scr;
116 }
117
132 void SPI_DeInit(void)
133 {
134 SPI->CR0 = 0x1C000000;
135 SPI->CR1 = 0x00000000;
136 SPI->CPSR = 0x00000000;
137 SPI->IMSC = 0x00000000;
138 SPI->ICR = 0x00000000;
139 SPI->DMACR = 0x00000000;
140 SPI->RXFRM = 0x00000000;
141 SPI->CHN = 0x00000000;
142 SPI->WDTXF = 0x00000000;
143 }
144
152 void SPI_Init(SPI_InitType* SPI_InitStruct)
153 {
154 /* check the parameters */
155 assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));
156 assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize));
157 assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));
158 assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));
159
160 /* Set the specified baud rate */
161 SPI_SetBaudrate(SPI_InitStruct->SPI_BaudRate);
162
163 /* Set SPI mode */
164 SPI->CR1_b.MS = SPI_InitStruct->SPI_Mode;
165
166 /* Set CPOL */
167 SPI->CR0_b.SPO = SPI_InitStruct->SPI_CPOL;
168
169 /* Set CPHA */
170 SPI->CR0_b.SPH = SPI_InitStruct->SPI_CPHA;
171
172 /* Set datasize */
173 SPI->CR0_b.DSS = SPI_InitStruct->SPI_DataSize;
174 }
175
176
182 void SPI_StructInit(SPI_InitType* SPI_InitStruct)
183 {
184 /* Initialize the SPI_Mode member */
185 SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;
186
187 /* Initialize the SPI_DataSize member */
188 SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;
189
190 /* Initialize the SPI_CPOL member */
191 SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;
192
193 /* Initialize the SPI_CPHA member */
194 SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;
195
196 /* Initialize the SPI_BaudRate member */
197 SPI_InitStruct->SPI_BaudRate = 1000000;
198 }
199
206 void SPI_Cmd(FunctionalState NewState)
207 {
208 /* Check the parameters */
209 assert_param(IS_FUNCTIONAL_STATE(NewState));
210
211 if (NewState != DISABLE) {
212 /* Enable the selected SPI peripheral */
213 SPI->CR1_b.SSE = SET;
214 }
215 else {
216 /* Disable the selected SPI peripheral */
217 SPI->CR1_b.SSE = RESET;
218 }
219 }
220
235 void SPI_ITConfig(uint8_t SPI_IT, FunctionalState NewState)
236 {
237 /* Check the parameters */
238 assert_param(IS_FUNCTIONAL_STATE(NewState));
239 assert_param(IS_SPI_CONFIG_IT(SPI_IT));
240
241 if (NewState != DISABLE) {
242 /* Enable the selected SPI interrupts */
243 SET_BIT(SPI->IMSC, SPI_IT);
244 }
245 else {
246 /* Disable the selected SPI interrupts */
247 CLEAR_BIT(SPI->IMSC, SPI_IT);
248 }
249 }
250
251
258 void SPI_SlaveModeOutputCmd(FunctionalState NewState)
259 {
260 /* Check the parameters */
261 assert_param(IS_FUNCTIONAL_STATE(NewState));
262
263 if (NewState != DISABLE) {
264 /* Enable the output */
265 SPI->CR1_b.SOD = RESET;
266 }
267 else {
268 /* Disable the output */
269 SPI->CR1_b.SOD = SET;
270 }
271 }
272
278 void SPI_SendData(uint32_t Data)
279 {
280 /* Write in the DR register the data to be sent */
281 SPI->DR = Data;
282 }
283
289 uint32_t SPI_ReceiveData(void)
290 {
291 /* Return the data in the DR register */
292 return SPI->DR;
293 }
294
305 void SPI_DataSizeConfig(uint16_t SPI_DataSize)
306 {
307 /* Check the parameters */
308 assert_param(IS_SPI_DATASIZE(SPI_DataSize));
309
310 /* set the datasize */
311 SPI->CR0_b.DSS = SPI_DataSize;
312 }
313
327 FlagStatus SPI_GetFlagStatus(uint16_t SPI_FLAG)
328 {
329 /* Check the parameters */
330 assert_param(IS_SPI_GET_FLAG(SPI_FLAG));
331
332 /* Check the status of the specified SPI flag */
333 if (READ_BIT(SPI->SR, SPI_FLAG) != (uint16_t)RESET) {
334 /* SPI_FLAG is set */
335 return SET;
336 }
337 else {
338 /* SPI_FLAG is reset */
339 return RESET;
340 }
341
342 }
343
357 ITStatus SPI_GetITStatus(uint8_t SPI_IT)
358 {
359 /* Check the parameters */
360 assert_param(IS_SPI_GET_IT(SPI_IT));
361
362 /* Check the status of the specified SPI interrupt */
363 if (READ_BIT(SPI->RIS, SPI_IT) != (uint16_t)RESET) {
364 /* SPI_IT is set */
365 return SET;
366 }
367 else {
368 /* SPI_IT is reset */
369 return RESET;
370 }
371
372 }
373
386 void SPI_ClearITPendingBit(uint8_t SPI_IT)
387 {
388 /* Check the parameters */
389 assert_param(IS_SPI_CLEAR_IT(SPI_IT));
390
391 /* Clear the selected SPI interrupt pending bit */
392 CLEAR_BIT(SPI->ICR, SPI_IT);
393 }
394
401 void SPI_ClearRXFIFO(void)
402 {
403 /* Flush the data from SPI RX FIFO */
404 while(SET == SPI_GetFlagStatus(SPI_FLAG_RNE) ) {
405 SPI_ReceiveData();
406 }
407 }
408
415 void SPI_ClearTXFIFO(void)
416 {
417 uint32_t tmp;
418
419 /* Enable read from the TX FIFO */
420 SPI->ITCR_b.SWAPFIFO = SET;
421
422 /* Flush the data from the TX FIFO till it is not empty. */
423 while(0 == SPI->SR_b.TFE) {
424 tmp |= SPI->TDR;
425 }
426
427 /* Disable the read from the TX FIFO */
428 SPI->ITCR_b.SWAPFIFO = RESET;
429
430 }
431
442 void SPI_SetMasterCommunicationMode(uint32_t Mode)
443 {
444 /* Check the parameters */
445 assert_param(IS_SPI_COM_MODE(Mode));
446
447 /* Set the communication mode */
448 SPI->CR0_b.SPIM = Mode;
449 }
450
456 void SPI_SetDummyCharacter(uint32_t NullCharacter)
457 {
458 /* Set the dummy character */
459 SPI->CHN = NullCharacter;
460 }
461
467 void SPI_SetNumFramesToReceive(uint16_t Number)
468 {
469 /* Set the number of frames to receive */
470 SPI->RXFRM = Number;
471 }
472
478 void SPI_SetNumFramesToTransmit(uint16_t Number)
479 {
480 /* Set the number of frames to transmit */
481 SPI->WDTXF = Number;
482 }
483
484
491 void SPI_SlaveSwSelection(FunctionalState NewState)
492 {
493 /* Check the parameters */
494 assert_param(IS_FUNCTIONAL_STATE(NewState));
495
496 if (NewState != DISABLE) {
497 /* Enable the output */
498 SPI->CR0_b.CS1 = RESET;
499 }
500 else {
501 /* Disable the output */
502 SPI->CR0_b.CS1 = SET;
503 }
504 }
505
511 void SPI_EndianFormatReception(uint8_t Endian)
512 {
513 /* Check the parameters */
514 assert_param(IS_SPI_ENDIAN(Endian));
515
516 SPI->CR1_b.RENDN = Endian;
517 }
518
524 void SPI_EndianFormatTransmission(uint8_t Endian)
525 {
526 /* Check the parameters */
527 assert_param(IS_SPI_ENDIAN(Endian));
528
529 SPI->CR1_b.TENDN = Endian;
530 }
531
532
544 void SPI_DelayBetweenFrames(uint8_t Delay)
545 {
546 /* Check the parameters */
547 assert_param(IS_SPI_ENDIAN(Delay));
548
549 SPI->CR1_b.MSPIWAIT = Delay;
550 }
551
552
559 void SPI_DelayDataInput(FunctionalState NewState)
560 {
561 /* Check the parameters */
562 assert_param(IS_FUNCTIONAL_STATE(NewState));
563
564 if (NewState != DISABLE) {
565 /* Enable the output */
566 SPI->CR1_b.DATAINDEL = RESET;
567 }
568 else {
569 /* Disable the output */
570 SPI->CR1_b.DATAINDEL = SET;
571 }
572 }
573
574
584 void SPI_TxFifoInterruptLevelConfig(uint8_t SPI_TX_FIFO_LEV)
585 {
586 /* Check the parameters */
587 assert_param(IS_SPI_FIFO_LEV(SPI_TX_FIFO_LEV));
588
589 SPI->CR1_b.TXIFLSEL = SPI_TX_FIFO_LEV;
590 }
591
602 void SPI_RxFifoInterruptLevelConfig(uint8_t SPI_RX_FIFO_LEV)
603 {
604 /* Check the parameters */
605 assert_param(IS_SPI_FIFO_LEV(SPI_RX_FIFO_LEV));
606
607 SPI->CR1_b.RXIFLSEL = SPI_RX_FIFO_LEV;
608 }
609
620 void SPI_DMACmd(uint8_t SPI_DMAReq, FunctionalState NewState)
621 {
622 /* Check the parameters */
623 assert_param(IS_SPI_DMAREQ(SPI_DMAReq));
624 assert_param(IS_FUNCTIONAL_STATE(NewState));
625
626 if (NewState != DISABLE)
627 {
628 /* Enable the DMA transfer */
629 SPI->DMACR |= SPI_DMAReq;
630 }
631 else
632 {
633 /* Disable the DMA transfer */
634 SPI->DMACR &= (uint8_t)~SPI_DMAReq;
635 }
636 }
637
650 /******************* (C) COPYRIGHT 2016 STMicroelectronics *****END OF FILE****/
SPI_DelayBetweenFrames
void SPI_DelayBetweenFrames(uint8_t Delay)
Configure the delay between the frames. The MSPIWAIT value is used to insert a wait state between fra...
Definition: BlueNRG1_spi.c:544
IS_SPI_CLEAR_IT
#define IS_SPI_CLEAR_IT(IT)
Definition: BlueNRG1_spi.h:212
SPI_CLOCK
#define SPI_CLOCK
Definition: BlueNRG1_spi.c:50
IS_SPI_CPHA
#define IS_SPI_CPHA(CPHA)
Definition: BlueNRG1_spi.h:189
SPI_FLAG_RNE
#define SPI_FLAG_RNE
Definition: BlueNRG1_spi.h:230
SPI_SetNumFramesToReceive
void SPI_SetNumFramesToReceive(uint16_t Number)
Set the number of frames to receive from slave.
Definition: BlueNRG1_spi.c:467
MIN_DIVIDER
#define MIN_DIVIDER
Definition: BlueNRG1_spi.c:47
MAX_SCR
#define MAX_SCR
Definition: BlueNRG1_spi.c:45
IS_SPI_FIFO_LEV
#define IS_SPI_FIFO_LEV(FIFO_LEV)
Definition: BlueNRG1_spi.h:266
SPI_SlaveModeOutputCmd
void SPI_SlaveModeOutputCmd(FunctionalState NewState)
Enables or disables the output if in slave mode.
Definition: BlueNRG1_spi.c:258
SPI_ClearTXFIFO
void SPI_ClearTXFIFO(void)
Clear all data present within the TX FIFO of the SPI peripherial. SPI peripherial clocks have to be e...
Definition: BlueNRG1_spi.c:415
SPI_DataSizeConfig
void SPI_DataSizeConfig(uint16_t SPI_DataSize)
Configures the data size for the selected SPI.
Definition: BlueNRG1_spi.c:305
IS_SPI_DMAREQ
#define IS_SPI_DMAREQ(DMAREQ)
Definition: BlueNRG1_spi.h:250
SPI_GetITStatus
ITStatus SPI_GetITStatus(uint8_t SPI_IT)
Checks whether the specified SPI interrupt has occurred or not.
Definition: BlueNRG1_spi.c:357
IS_SPI_CPOL
#define IS_SPI_CPOL(CPOL)
Definition: BlueNRG1_spi.h:173
SPI_CPOL_Low
#define SPI_CPOL_Low
Definition: BlueNRG1_spi.h:169
SPI_SetNumFramesToTransmit
void SPI_SetNumFramesToTransmit(uint16_t Number)
Set the number of frames to transmit to slave.
Definition: BlueNRG1_spi.c:478
SPI_InitType
Structure definition of SPI initialization.
Definition: BlueNRG1_spi.h:49
SPI_InitType::SPI_Mode
uint8_t SPI_Mode
Definition: BlueNRG1_spi.h:50
IS_SPI_BAUDRATE
#define IS_SPI_BAUDRATE(BAUDRATE)
Definition: BlueNRG1_spi.h:84
IS_SPI_COM_MODE
#define IS_SPI_COM_MODE(MODE)
Definition: BlueNRG1_spi.h:99
SPI_InitType::SPI_CPHA
uint8_t SPI_CPHA
Definition: BlueNRG1_spi.h:59
SPI_ClearITPendingBit
void SPI_ClearITPendingBit(uint8_t SPI_IT)
Clears the SPI interrupt pending bits.
Definition: BlueNRG1_spi.c:386
SPI_SetDummyCharacter
void SPI_SetDummyCharacter(uint32_t NullCharacter)
Set the dummy character used for the SPI master communication.
Definition: BlueNRG1_spi.c:456
IS_SPI_DATASIZE
#define IS_SPI_DATASIZE(DATASIZE)
Definition: BlueNRG1_spi.h:159
SPI_DelayDataInput
void SPI_DelayDataInput(FunctionalState NewState)
Master insert a delay of two clock cycle if enabled.
Definition: BlueNRG1_spi.c:559
SPI_StructInit
void SPI_StructInit(SPI_InitType *SPI_InitStruct)
Fills each SPI_InitStruct member with its default value.
Definition: BlueNRG1_spi.c:182
SPI_DMACmd
void SPI_DMACmd(uint8_t SPI_DMAReq, FunctionalState NewState)
Enables or disables the SPI DMA interface.
Definition: BlueNRG1_spi.c:620
SPI_RxFifoInterruptLevelConfig
void SPI_RxFifoInterruptLevelConfig(uint8_t SPI_RX_FIFO_LEV)
Sets the SPI interrupt FIFO level.
Definition: BlueNRG1_spi.c:602
SPI_InitType::SPI_CPOL
uint8_t SPI_CPOL
Definition: BlueNRG1_spi.h:56
IS_SPI_ENDIAN
#define IS_SPI_ENDIAN(FORMAT)
Definition: BlueNRG1_spi.h:285
SPI_InitType::SPI_DataSize
uint8_t SPI_DataSize
Definition: BlueNRG1_spi.h:53
SPI_ITConfig
void SPI_ITConfig(uint8_t SPI_IT, FunctionalState NewState)
Enables or disables the specified SPI interrupts.
Definition: BlueNRG1_spi.c:235
IS_SPI_MODE
#define IS_SPI_MODE(MODE)
Definition: BlueNRG1_spi.h:117
SPI_InitType::SPI_BaudRate
uint32_t SPI_BaudRate
Definition: BlueNRG1_spi.h:62
SPI_Mode_Slave
#define SPI_Mode_Slave
Definition: BlueNRG1_spi.h:114
BlueNRG1_spi.h
This file contains all the functions prototypes for the SPI firmware library.
SPI_SlaveSwSelection
void SPI_SlaveSwSelection(FunctionalState NewState)
Master can select the slave by driving the CS pin by software.
Definition: BlueNRG1_spi.c:491
SPI_DeInit
void SPI_DeInit(void)
Deinitializes the SPI peripheral registers to their default reset values.
Definition: BlueNRG1_spi.c:132
SPI_SetMasterCommunicationMode
void SPI_SetMasterCommunicationMode(uint32_t Mode)
Set the SPI communication mode.
Definition: BlueNRG1_spi.c:442
SPI_SendData
void SPI_SendData(uint32_t Data)
Transmits a Data through the SPI peripheral.
Definition: BlueNRG1_spi.c:278
SPI_ClearRXFIFO
void SPI_ClearRXFIFO(void)
Clear all data present within the RX FIFO of the SPI peripherial. SPI peripherial clocks have to be e...
Definition: BlueNRG1_spi.c:401
SPI_CPHA_1Edge
#define SPI_CPHA_1Edge
Definition: BlueNRG1_spi.h:185
SPI_SetBaudrate
void SPI_SetBaudrate(uint32_t Baudrate)
SPI set baud rate function.
Definition: BlueNRG1_spi.c:90
SPI_Cmd
void SPI_Cmd(FunctionalState NewState)
Enables or disables the SPI peripheral.
Definition: BlueNRG1_spi.c:206
SPI_ReceiveData
uint32_t SPI_ReceiveData(void)
Returns the most recent received data by the SPI peripheral.
Definition: BlueNRG1_spi.c:289
SPI_TxFifoInterruptLevelConfig
void SPI_TxFifoInterruptLevelConfig(uint8_t SPI_TX_FIFO_LEV)
Sets the SPI interrupt FIFO level.
Definition: BlueNRG1_spi.c:584
IS_SPI_GET_IT
#define IS_SPI_GET_IT(IT)
Definition: BlueNRG1_spi.h:216
MAX_DIVIDER
#define MAX_DIVIDER
Definition: BlueNRG1_spi.c:48
SPI_DataSize_8b
#define SPI_DataSize_8b
Definition: BlueNRG1_spi.h:152
SPI_GetFlagStatus
FlagStatus SPI_GetFlagStatus(uint16_t SPI_FLAG)
Checks whether the specified SPI flag is set or not.
Definition: BlueNRG1_spi.c:327
IS_SPI_GET_FLAG
#define IS_SPI_GET_FLAG(FLAG)
Definition: BlueNRG1_spi.h:235
IS_SPI_CONFIG_IT
#define IS_SPI_CONFIG_IT(IT)
Definition: BlueNRG1_spi.h:208
SPI_EndianFormatTransmission
void SPI_EndianFormatTransmission(uint8_t Endian)
Master can select the slave by driving the CS pin by software.
Definition: BlueNRG1_spi.c:524
SPI_Init
void SPI_Init(SPI_InitType *SPI_InitStruct)
Initializes the SPI peripheral according to the specified parameters in the SPI_InitStruct.
Definition: BlueNRG1_spi.c:152
SPI_EndianFormatReception
void SPI_EndianFormatReception(uint8_t Endian)
Master can select the slave by driving the CS pin by software.
Definition: BlueNRG1_spi.c:511