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BlueNRG1_dma.c
Go to the documentation of this file.
1
22 /* Includes ------------------------------------------------------------------*/
23 #include "BlueNRG1_dma.h"
24
45 /* DMA registers Masks */
46 #define CCR_CLEAR_MASK ((uint32_t)0xFFFF800F)
47
56 /* DMA Channelx interrupt pending bit masks */
57 #define DMA_CHANNEL0_FLAG_MASK ((uint32_t)(DMA_FLAG_GL0 | DMA_FLAG_TC0 | DMA_FLAG_HT0 | DMA_FLAG_TE0))
58 #define DMA_CHANNEL1_FLAG_MASK ((uint32_t)(DMA_FLAG_GL1 | DMA_FLAG_TC1 | DMA_FLAG_HT1 | DMA_FLAG_TE1))
59 #define DMA_CHANNEL2_FLAG_MASK ((uint32_t)(DMA_FLAG_GL2 | DMA_FLAG_TC2 | DMA_FLAG_HT2 | DMA_FLAG_TE2))
60 #define DMA_CHANNEL3_FLAG_MASK ((uint32_t)(DMA_FLAG_GL3 | DMA_FLAG_TC3 | DMA_FLAG_HT3 | DMA_FLAG_TE3))
61 #define DMA_CHANNEL4_FLAG_MASK ((uint32_t)(DMA_FLAG_GL4 | DMA_FLAG_TC4 | DMA_FLAG_HT4 | DMA_FLAG_TE4))
62 #define DMA_CHANNEL5_FLAG_MASK ((uint32_t)(DMA_FLAG_GL5 | DMA_FLAG_TC5 | DMA_FLAG_HT5 | DMA_FLAG_TE5))
63 #define DMA_CHANNEL6_FLAG_MASK ((uint32_t)(DMA_FLAG_GL6 | DMA_FLAG_TC6 | DMA_FLAG_HT6 | DMA_FLAG_TE6))
64 #define DMA_CHANNEL7_FLAG_MASK ((uint32_t)(DMA_FLAG_GL7 | DMA_FLAG_TC7 | DMA_FLAG_HT7 | DMA_FLAG_TE7))
65
66
67 #define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA_CH0) || \
68 ((PERIPH) == DMA_CH1) || \
69 ((PERIPH) == DMA_CH2) || \
70 ((PERIPH) == DMA_CH3) || \
71 ((PERIPH) == DMA_CH4) || \
72 ((PERIPH) == DMA_CH5) || \
73 ((PERIPH) == DMA_CH6) || \
74 ((PERIPH) == DMA_CH7))
75
116 void DMA_DeInit(DMA_CH_Type* DMAy_Channelx)
117 {
118 /* Check the parameters */
119 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
120
121 /* Disable the selected DMAy Channelx */
122 DMAy_Channelx->CCR_b.EN = RESET;
123
124 /* Reset DMAy Channelx control register */
125 DMAy_Channelx->CCR = 0;
126
127 /* Reset DMAy Channelx remaining bytes register */
128 DMAy_Channelx->CNDTR = 0;
129
130 /* Reset DMAy Channelx peripheral address register */
131 DMAy_Channelx->CPAR = 0;
132
133 /* Reset DMAy Channelx memory address register */
134 DMAy_Channelx->CMAR = 0;
135
136 if (DMAy_Channelx == DMA_CH1)
137 {
138 /* Reset interrupt pending bits for DMA Channel1 */
139 SET_BIT(DMA->IFCR, DMA_CHANNEL1_FLAG_MASK);
140 }
141 else if (DMAy_Channelx == DMA_CH2)
142 {
143 /* Reset interrupt pending bits for DMA Channel2 */
144 SET_BIT(DMA->IFCR, DMA_CHANNEL2_FLAG_MASK);
145 }
146 else if (DMAy_Channelx == DMA_CH3)
147 {
148 /* Reset interrupt pending bits for DMA Channel3 */
149 SET_BIT(DMA->IFCR, DMA_CHANNEL3_FLAG_MASK);
150 }
151 else if (DMAy_Channelx == DMA_CH4)
152 {
153 /* Reset interrupt pending bits for DMA Channel4 */
154 SET_BIT(DMA->IFCR, DMA_CHANNEL4_FLAG_MASK);
155 }
156 else if (DMAy_Channelx == DMA_CH5)
157 {
158 /* Reset interrupt pending bits for DMA Channel5 */
159 SET_BIT(DMA->IFCR, DMA_CHANNEL5_FLAG_MASK);
160 }
161 else if (DMAy_Channelx == DMA_CH6)
162 {
163 /* Reset interrupt pending bits for DMA Channel6 */
164 SET_BIT(DMA->IFCR, DMA_CHANNEL6_FLAG_MASK);
165 }
166 else if (DMAy_Channelx == DMA_CH7)
167 {
168 /* Reset interrupt pending bits for DMA Channel7 */
169 SET_BIT(DMA->IFCR, DMA_CHANNEL7_FLAG_MASK);
170 }
171 }
172
182 void DMA_Init(DMA_CH_Type* DMAy_Channelx, DMA_InitType* DMA_InitStruct)
183 {
184 uint32_t tmpreg = 0;
185
186 /* Check the parameters */
187 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
188 assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
189 assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));
190 assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
191 assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));
192 assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
193 assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
194 assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
195 assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
196 assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));
197
198 /*--------------------------- DMAy Channelx CCR Configuration -----------------*/
199 /* Get the DMAy_Channelx CCR value */
200 tmpreg = DMAy_Channelx->CCR;
201 /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
202 tmpreg &= CCR_CLEAR_MASK;
203 /* Configure DMAy Channelx: data transfer, data size, priority level and mode */
204 /* Set DIR bit according to DMA_DIR value */
205 /* Set CIRC bit according to DMA_Mode value */
206 /* Set PINC bit according to DMA_PeripheralInc value */
207 /* Set MINC bit according to DMA_MemoryInc value */
208 /* Set PSIZE bits according to DMA_PeripheralDataSize value */
209 /* Set MSIZE bits according to DMA_MemoryDataSize value */
210 /* Set PL bits according to DMA_Priority value */
211 /* Set the MEM2MEM bit according to DMA_M2M value */
212 tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
213 DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
214 DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
215 DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
216
217 /* Write to DMAy Channelx CCR */
218 DMAy_Channelx->CCR = tmpreg;
219
220 /*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
221 /* Write to DMAy Channelx CNDTR */
222 DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;
223
224 /*--------------------------- DMAy Channelx CPAR Configuration ----------------*/
225 /* Write to DMAy Channelx CPAR */
226 DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
227
228 /*--------------------------- DMAy Channelx CMAR Configuration ----------------*/
229 /* Write to DMAy Channelx CMAR */
230 DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;
231 }
232
239 void DMA_StructInit(DMA_InitType* DMA_InitStruct)
240 {
241 /*-------------- Reset DMA init structure parameters values ------------------*/
242 /* Initialize the DMA_PeripheralBaseAddr member */
243 DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
244 /* Initialize the DMA_MemoryBaseAddr member */
245 DMA_InitStruct->DMA_MemoryBaseAddr = 0;
246 /* Initialize the DMA_DIR member */
247 DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
248 /* Initialize the DMA_BufferSize member */
249 DMA_InitStruct->DMA_BufferSize = 0;
250 /* Initialize the DMA_PeripheralInc member */
251 DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
252 /* Initialize the DMA_MemoryInc member */
253 DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
254 /* Initialize the DMA_PeripheralDataSize member */
255 DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
256 /* Initialize the DMA_MemoryDataSize member */
257 DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
258 /* Initialize the DMA_Mode member */
259 DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
260 /* Initialize the DMA_Priority member */
261 DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
262 /* Initialize the DMA_M2M member */
263 DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
264 }
265
274 void DMA_Cmd(DMA_CH_Type* DMAy_Channelx, FunctionalState NewState)
275 {
276 /* Check the parameters */
277 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
278 assert_param(IS_FUNCTIONAL_STATE(NewState));
279
280 if (NewState != DISABLE) {
281 /* Enable the selected DMAy Channelx */
282 DMAy_Channelx->CCR_b.EN = SET;
283 }
284 else {
285 /* Disable the selected DMAy Channelx */
286 DMAy_Channelx->CCR_b.EN = RESET;
287 }
288 }
289
290
298 void DMA_SelectAdcChannel(uint8_t DMA_AdcChannel, FunctionalState NewState)
299 {
300 /* Check the parameters */
301 assert_param(IS_DMA_ADC_CH(DMA_AdcChannel));
302 assert_param(IS_FUNCTIONAL_STATE(NewState));
303
304 if (NewState != DISABLE) {
305 /* Enable the selected of DMA ADC Channel */
306 SET_BIT(CKGEN_SOC->DMA_CONFIG, DMA_AdcChannel);
307 }
308 else {
309 /* Disable the selected of DMA ADC Channel */
310 CLEAR_BIT(CKGEN_SOC->DMA_CONFIG, DMA_AdcChannel);
311 }
312 }
313
314
324 void DMA_SetCurrDataCounter(DMA_CH_Type* DMAy_Channelx, uint16_t DataNumber)
325 {
326 /* Check the parameters */
327 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
328
329 /*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
330 /* Write to DMAy Channelx CNDTR */
331 DMAy_Channelx->CNDTR = (uint32_t)DataNumber;
332 }
333
342 uint16_t DMA_GetCurrDataCounter(DMA_CH_Type* DMAy_Channelx)
343 {
344 /* Check the parameters */
345 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
346 /* Return the number of remaining data units for DMAy Channelx */
347 return ((uint16_t)(DMAy_Channelx->CNDTR));
348 }
349
364 void DMA_FlagConfig(DMA_CH_Type* DMAy_Channelx, uint32_t DMA_Flag, FunctionalState NewState)
365 {
366 /* Check the parameters */
367 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
368 assert_param(IS_DMA_CONFIG_FLAG(DMA_Flag));
369 assert_param(IS_FUNCTIONAL_STATE(NewState));
370
371 if (NewState != DISABLE) {
372 /* Enable the selected DMA interrupts */
373 SET_BIT(DMAy_Channelx->CCR, DMA_Flag);
374 }
375 else {
376 /* Disable the selected DMA interrupts */
377 CLEAR_BIT(DMAy_Channelx->CCR, DMA_Flag);
378 }
379 }
380
422 FlagStatus DMA_GetFlagStatus(uint32_t DMA_Flag)
423 {
424 uint32_t tmpreg = 0;
425
426 /* Check the parameters */
427 assert_param(IS_DMA_CH_FLAG(DMA_Flag));
428
429 /* Get DMA ISR register value */
430 tmpreg = DMA->ISR;
431
432 /* Check the status of the specified DMA flag */
433 if ((tmpreg & DMA_Flag) != (uint32_t)RESET)
434 {
435 /* DMA_Flag is set */
436 return SET;
437 }
438 else
439 {
440 /* DMA_Flag is reset */
441 return RESET;
442 }
443
444 }
445
446
487 void DMA_ClearFlag(uint32_t DMA_Flag)
488 {
489 /* Check the parameters */
490 assert_param(IS_DMA_CH_FLAG(DMA_Flag));
491
492 /* Clear the selected DMA flags */
493 DMA->IFCR = DMA_Flag;
494
495 }
496
513 /******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/
DMA_MemoryInc_Disable
#define DMA_MemoryInc_Disable
Definition: BlueNRG1_dma.h:124
DMA_ClearFlag
void DMA_ClearFlag(uint32_t DMA_Flag)
Clears the DMAy Channelx's pending flags.
Definition: BlueNRG1_dma.c:487
DMA_CHANNEL7_FLAG_MASK
#define DMA_CHANNEL7_FLAG_MASK
Definition: BlueNRG1_dma.c:64
DMA_Priority_Low
#define DMA_Priority_Low
Definition: BlueNRG1_dma.h:177
IS_DMA_MODE
#define IS_DMA_MODE(MODE)
Definition: BlueNRG1_dma.h:165
DMA_CHANNEL2_FLAG_MASK
#define DMA_CHANNEL2_FLAG_MASK
Definition: BlueNRG1_dma.c:59
IS_DMA_PRIORITY
#define IS_DMA_PRIORITY(PRIORITY)
Definition: BlueNRG1_dma.h:178
DMA_DeInit
void DMA_DeInit(DMA_CH_Type *DMAy_Channelx)
Deinitializes the DMAy Channelx registers to their default reset values.
Definition: BlueNRG1_dma.c:116
DMA_InitType::DMA_PeripheralInc
uint32_t DMA_PeripheralInc
Definition: BlueNRG1_dma.h:62
DMA_GetFlagStatus
FlagStatus DMA_GetFlagStatus(uint32_t DMA_Flag)
Checks whether the specified DMAy Channelx flag is set or not.
Definition: BlueNRG1_dma.c:422
DMA_InitType::DMA_PeripheralDataSize
uint32_t DMA_PeripheralDataSize
Definition: BlueNRG1_dma.h:68
DMA_Mode_Normal
#define DMA_Mode_Normal
Definition: BlueNRG1_dma.h:164
DMA_PeripheralDataSize_Byte
#define DMA_PeripheralDataSize_Byte
Definition: BlueNRG1_dma.h:135
DMA_CHANNEL6_FLAG_MASK
#define DMA_CHANNEL6_FLAG_MASK
Definition: BlueNRG1_dma.c:63
IS_DMA_MEMORY_DATA_SIZE
#define IS_DMA_MEMORY_DATA_SIZE(SIZE)
Definition: BlueNRG1_dma.h:152
CCR_CLEAR_MASK
#define CCR_CLEAR_MASK
Definition: BlueNRG1_dma.c:46
IS_DMA_MEMORY_INC_STATE
#define IS_DMA_MEMORY_INC_STATE(STATE)
Definition: BlueNRG1_dma.h:125
DMA_SelectAdcChannel
void DMA_SelectAdcChannel(uint8_t DMA_AdcChannel, FunctionalState NewState)
Enables or disables the specified DMA ADC Channel.
Definition: BlueNRG1_dma.c:298
DMA_Init
void DMA_Init(DMA_CH_Type *DMAy_Channelx, DMA_InitType *DMA_InitStruct)
Initializes the DMAy Channelx according to the specified parameters in the DMA_InitStruct.
Definition: BlueNRG1_dma.c:182
DMA_InitType::DMA_Mode
uint32_t DMA_Mode
Definition: BlueNRG1_dma.h:74
IS_DMA_PERIPHERAL_DATA_SIZE
#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE)
Definition: BlueNRG1_dma.h:138
DMA_InitType::DMA_Priority
uint32_t DMA_Priority
Definition: BlueNRG1_dma.h:79
DMA_InitType::DMA_M2M
uint32_t DMA_M2M
Definition: BlueNRG1_dma.h:82
DMA_CHANNEL5_FLAG_MASK
#define DMA_CHANNEL5_FLAG_MASK
Definition: BlueNRG1_dma.c:62
DMA_PeripheralInc_Disable
#define DMA_PeripheralInc_Disable
Definition: BlueNRG1_dma.h:112
DMA_SetCurrDataCounter
void DMA_SetCurrDataCounter(DMA_CH_Type *DMAy_Channelx, uint16_t DataNumber)
Sets the number of data units in the current DMAy Channelx transfer.
Definition: BlueNRG1_dma.c:324
DMA_InitType::DMA_DIR
uint32_t DMA_DIR
Definition: BlueNRG1_dma.h:55
IS_DMA_ALL_PERIPH
#define IS_DMA_ALL_PERIPH(PERIPH)
Definition: BlueNRG1_dma.c:67
IS_DMA_CONFIG_FLAG
#define IS_DMA_CONFIG_FLAG(FLAG)
Definition: BlueNRG1_dma.h:205
DMA_Cmd
void DMA_Cmd(DMA_CH_Type *DMAy_Channelx, FunctionalState NewState)
Enables or disables the specified DMAy Channelx.
Definition: BlueNRG1_dma.c:274
DMA_InitType::DMA_PeripheralBaseAddr
uint32_t DMA_PeripheralBaseAddr
Definition: BlueNRG1_dma.h:51
DMA_CHANNEL4_FLAG_MASK
#define DMA_CHANNEL4_FLAG_MASK
Definition: BlueNRG1_dma.c:61
DMA_FlagConfig
void DMA_FlagConfig(DMA_CH_Type *DMAy_Channelx, uint32_t DMA_Flag, FunctionalState NewState)
Enables or disables the specified DMAy Channelx interrupts.
Definition: BlueNRG1_dma.c:364
DMA_MemoryDataSize_Byte
#define DMA_MemoryDataSize_Byte
Definition: BlueNRG1_dma.h:149
DMA_GetCurrDataCounter
uint16_t DMA_GetCurrDataCounter(DMA_CH_Type *DMAy_Channelx)
Returns the number of remaining data units in the current DMAy Channelx transfer. ...
Definition: BlueNRG1_dma.c:342
DMA_CHANNEL3_FLAG_MASK
#define DMA_CHANNEL3_FLAG_MASK
Definition: BlueNRG1_dma.c:60
IS_DMA_PERIPHERAL_INC_STATE
#define IS_DMA_PERIPHERAL_INC_STATE(STATE)
Definition: BlueNRG1_dma.h:113
BlueNRG1_dma.h
This file contains all the functions prototypes for the DMA firmware library.
DMA_InitType::DMA_BufferSize
uint32_t DMA_BufferSize
Definition: BlueNRG1_dma.h:58
DMA_CHANNEL1_FLAG_MASK
#define DMA_CHANNEL1_FLAG_MASK
Definition: BlueNRG1_dma.c:58
DMA_InitType
DMA Init structure definition.
Definition: BlueNRG1_dma.h:49
DMA_InitType::DMA_MemoryDataSize
uint32_t DMA_MemoryDataSize
Definition: BlueNRG1_dma.h:71
DMA_DIR_PeripheralSRC
#define DMA_DIR_PeripheralSRC
Definition: BlueNRG1_dma.h:100
IS_DMA_CH_FLAG
#define IS_DMA_CH_FLAG(FLAG)
Definition: BlueNRG1_dma.h:250
IS_DMA_M2M_STATE
#define IS_DMA_M2M_STATE(STATE)
Definition: BlueNRG1_dma.h:192
IS_DMA_ADC_CH
#define IS_DMA_ADC_CH(SEL)
Definition: BlueNRG1_dma.h:274
DMA_InitType::DMA_MemoryBaseAddr
uint32_t DMA_MemoryBaseAddr
Definition: BlueNRG1_dma.h:53
DMA_M2M_Disable
#define DMA_M2M_Disable
Definition: BlueNRG1_dma.h:191
IS_DMA_DIR
#define IS_DMA_DIR(DIR)
Definition: BlueNRG1_dma.h:101
DMA_StructInit
void DMA_StructInit(DMA_InitType *DMA_InitStruct)
Fills each DMA_InitStruct member with its default value.
Definition: BlueNRG1_dma.c:239
IS_DMA_BUFFER_SIZE
#define IS_DMA_BUFFER_SIZE(SIZE)
Definition: BlueNRG1_dma.h:295
DMA_InitType::DMA_MemoryInc
uint32_t DMA_MemoryInc
Definition: BlueNRG1_dma.h:65