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lsm6ds3.h File Reference

This file contains definitions for the lsm6ds3.c firmware driver. More...

`#include <stdint.h>`

Go to the source code of this file.

## Classes

struct | IMU_6AXES_InitTypeDef
| IMU_6AXES init structure definition. More...
struct | IMU_6AXES_DrvTypeDef
| IMU_6AXES driver structure definition. More...
struct | LSM6DS3_DrvExtTypeDef
| LSM6DS3 driver extended internal structure definition. More...

## Macros

#define | NULL (void *) 0
#define | LSM6DS3_XG_FUNC_CFG_ACCESS 0x01
| FIFO control register. More...
#define | LSM6DS3_XG_SENSOR_SYNC_TIME_FRAME 0x04
| FIFO control register. More...
#define | LSM6DS3_XG_SENSOR_SYNC_ENABLE 0x05
| FIFO control register. More...
#define | LSM6DS3_XG_FIFO_CTRL1 0x06
| FIFO control register. More...
#define | LSM6DS3_XG_FIFO_CTRL2 0x07
| FIFO control register. More...
#define | LSM6DS3_XG_FIFO_CTRL3 0x08
| FIFO control register. More...
#define | LSM6DS3_XG_FIFO_CTRL4 0x09
| FIFO control register. More...
#define | LSM6DS3_XG_FIFO_CTRL5 0x0A
| FIFO control register. More...
#define | LSM6DS3_XG_ORIENT_CFG_G 0x0B
| Angular rate sensor sign and orientation register. More...
#define | LSM6DS3_XG_INT1_CTRL 0x0D
| INT1 pad control registrer. More...
#define | LSM6DS3_XG_INT2_CTRL 0x0E
| INT2 pad control registrer. More...
#define | LSM6DS3_XG_WHO_AM_I_ADDR 0x0F
| Device identifier register. More...
#define | LSM6DS3_XG_CTRL3_C 0x12
| Control Register 3. More...
#define | LSM6DS3_XG_CTRL4_C 0x13
| Control Register 4. More...
#define | LSM6DS3_XG_CTRL5_C 0x14
| Control Register 4. More...
#define | LSM6DS3_XG_CTRL10_C 0x19
| Control Register 10. More...
#define | LSM6DS3_XG_MASTER_CONFIG 0x1A
| Sensor hub Master config Register. More...
#define | LSM6DS3_XG_WAKE_UP_SRC 0x1B
| Wake up interrupt source register. More...
#define | LSM6DS3_XG_TAP_SRC 0x1C
| Tap source register. More...
#define | LSM6DS3_XG_D6D_SRC 0x1D
| Portrait, landscape face-up and face-down source register. More...
#define | LSM6DS3_XG_STATUS_REG 0x1E
| Status register. More...
#define | LSM6DS3_XG_FIFO_STATUS1 0x3A
| FIFO status control register. More...
#define | LSM6DS3_XG_FIFO_STATUS2 0x3B
| FIFO status control register (r). For a proper reading of the register it is suggested to set BDU bit in CTRL3_C (12h) to 0. More...
#define | LSM6DS3_XG_FIFO_STATUS3 0x3C
| FIFO status control register (r). For a proper reading of the register it is suggested to set BDU bit in CTRL3_C (12h) to 0. More...
#define | LSM6DS3_XG_FIFO_STATUS4 0x3D
| FIFO status control register (r). For a proper reading of the register it is suggested to set BDU bit in CTRL3_C (12h) to 0. More...
#define | LSM6DS3_XG_FIFO_STATUS4 0x3D
| FIFO status control register (r). For a proper reading of the register it is suggested to set BDU bit in CTRL3_C (12h) to 0. More...
#define | LSM6DS3_XG_FIFO_DATA_OUT_L 0x3E
| FIFO data output register (r). For a proper reading of the register it is suggested to set BDU bit in CTRL3_C (12h) to 0. More...
#define | LSM6DS3_XG_FIFO_DATA_OUT_H 0x3F
| FIFO data output register (r). For a proper reading of the register it is suggested to set BDU bit in CTRL3_C (12h) to 0. More...
#define | LSM6DS3_XG_TIMESTAMP0_REG 0x40
| Time stamp first byte data output register (r). The value is expressed as 24 bit and the bit resolution is defined by setting value in WAKE_UP_DUR (5Ch). More...
#define | LSM6DS3_XG_TIMESTAMP1_REG 0x41
| Time stamp second byte data output register (r). The value is expressed as 24 bit and the bit resolution is defined by setting value in WAKE_UP_DUR (5Ch). More...
#define | LSM6DS3_XG_TIMESTAMP2_REG 0x42
| Time stamp third byte data output register (r). The value is expressed as 24 bit and the bit resolution is defined by setting value in WAKE_UP_DUR (5Ch). More...
#define | LSM6DS3_XG_STEP_COUNTER_L 0x4B
| Step counter output register (r). More...
#define | LSM6DS3_XG_STEP_COUNTER_H 0x4C
| Step counter output register (r). More...
#define | LSM6DS3_XG_FUNC_SRC 0x53
| Significant motion, tilt, step detector, soft iron and sensor hub interrupt source register. More...
#define | LSM6DS3_XG_TAP_CFG 0x58
| Time stamp, pedometer, tilt, filtering, and tap recognition functions configuration register. More...
#define | LSM6DS3_XG_TAP_THS_6D 0x59
| Portrait/landscape position and tap function threshold register. More...
#define | LSM6DS3_XG_INT_DUR2 0x5A
| Tap recognition function setting register (r/w) More...
#define | LSM6DS3_XG_WAKE_UP_THS 0x5B
| Tap recognition function setting register. More...
#define | LSM6DS3_XG_WAKE_UP_DUR 0x5C
| Free-fall, wake-up, time stamp and sleep mode functions duration setting register (r/w). More...
#define | LSM6DS3_XG_WAKE_FREE_FALL 0x5D
| Free-fall function duration setting register. More...
#define | LSM6DS3_XG_MD1_CFG 0x5E
| Functions routing on INT1 register. More...
#define | LSM6DS3_XG_MD2_CFG 0x5F
| Functions routing on INT2 register. More...
#define | LSM6DS3_XG_SENSORHUB1_REG 0x2E
| SENSORHUB REGISTER 1 : SLV0 first external sensor, first axis output register (r). The value is expressed as 16bit word in two’s complement. More...
#define | LSM6DS3_XG_SENSORHUB2_REG 0x2F
| SENSORHUB REGISTER 2 : SLV0 first external sensor, first axis output register (r). The value is expressed as 16bit word in two’s complement. More...
#define | LSM6DS3_XG_SENSORHUB3_REG 0x30
| SENSORHUB REGISTER 3 : SLV0 first external sensor, second axis output register (r). The value is expressed as 16bit word in two’s complement. More...
#define | LSM6DS3_XG_SENSORHUB4_REG 0x31
| SENSORHUB REGISTER 4 : SLV0 first external sensor, second axis output register (r). The value is expressed as 16bit word in two’s complement. More...
#define | LSM6DS3_XG_SENSORHUB5_REG 0x32
| SENSORHUB REGISTER 5 : SLV0 first external sensor, third axis output register (r). The value is expressed as 16bit word in two’s complement. More...
#define | LSM6DS3_XG_SENSORHUB6_REG 0x33
| SENSORHUB REGISTER 6 : SLV0 first external sensor, third axis output register (r). The value is expressed as 16bit word in two’s complement. More...
#define | LSM6DS3_XG_SENSORHUB7_REG 0x34
| SENSORHUB REGISTER 7 : SLV1 second external sensor, first axis output register (r). The value is expressed as 16bit word in two’s complement. More...
#define | LSM6DS3_XG_SENSORHUB8_REG 0x35
| SENSORHUB REGISTER 8 : SLV1 second external sensor, first axis output register (r). The value is expressed as 16bit word in two’s complement. More...
#define | LSM6DS3_XG_SENSORHUB9_REG 0x36
| SENSORHUB REGISTER 9 : SLV1 second external sensor,, second axis output register (r). The value is expressed as 16bit word in two’s complement. More...
#define | LSM6DS3_XG_SENSORHUB10_REG 0x37
| SLV1 second external sensor, second axis output register (r). The value is expressed as 16bit word in two’s complement. More...
#define | LSM6DS3_XG_SENSORHUB11_REG 0x38
| SLV1 second external sensor, third axis output register (r). The value is expressed as 16bit word in two’s complement. More...
#define | LSM6DS3_XG_SENSORHUB12_REG 0x39
| SLV1 second external sensor, third axis output register (r). The value is expressed as 16bit word in two’s complement. More...
#define | LSM6DS3_XG_CTRL2_G 0x11
| Angular rate sensor Control Register 2. More...
#define | LSM6DS3_XG_CTRL6_G 0x15
| Angular rate sensor Control Register 6. More...
#define | LSM6DS3_XG_CTRL7_G 0x16
| Angular rate sensor Control Register 7. More...
#define | LSM6DS3_XG_OUT_X_L_G 0x22
| Gyroscope data (LSB) More...
#define | LSM6DS3_XG_OUT_X_H_G 0x23
| Gyroscope data (MSB) More...
#define | LSM6DS3_XG_OUT_Y_L_G 0x24
| Gyroscope data (LSB) More...
#define | LSM6DS3_XG_OUT_Y_H_G 0x25
| Gyroscope data (MSB) More...
#define | LSM6DS3_XG_OUT_Z_L_G 0x26
| Gyroscope data (LSB) More...
#define | LSM6DS3_XG_OUT_Z_H_G 0x27
| Gyroscope data (MSB) More...
#define | LSM6DS3_XG_CTRL1_XL 0x10
| Linear acceleration sensor Control Register 1. More...
#define | LSM6DS3_XG_CTRL8_XL 0x17
| XL sensor Control Register 8. More...
#define | LSM6DS3_XG_CTRL9_XL 0x18
| Linear acceleration sensor Control Register 9. More...
#define | LSM6DS3_XG_OUT_X_L_XL 0x28
| Accelerometer data (LSB) More...
#define | LSM6DS3_XG_OUT_X_H_XL 0x29
| Accelerometer data (MSB) More...
#define | LSM6DS3_XG_OUT_Y_L_XL 0x2A
| Accelerometer data (LSB) More...
#define | LSM6DS3_XG_OUT_Y_H_XL 0x2B
| Accelerometer data (MSB) More...
#define | LSM6DS3_XG_OUT_Z_L_XL 0x2C
| Accelerometer data (LSB) More...
#define | LSM6DS3_XG_OUT_Z_H_XL 0x2D
| Accelerometer data (MSB) More...
#define | LSM6DS3_ADDRESS_LOW 0xD4
| Device Address. More...
#define | LSM6DS3_ADDRESS_HIGH 0xD6
#define | LSM6DS3_XG_MEMS_ADDRESS LSM6DS3_ADDRESS_LOW
#define | I_AM_LSM6DS3_XG ((uint8_t)0x69)
| Device Identifier. Default value of the WHO_AM_I register. More...
#define | LSM6DS3_XG_IF_INC ((uint8_t)0x04)
| Register address automatically incremented during a multiple byte access with a serial interface (I2C or SPI). Default value of the LSM6DS3_XG_CTRL3_C register. More...
#define | LSM6DS3_XG_IF_INC_MASK ((uint8_t)0x04)
#define | LSM6DS3_XG_FIFO_ODR_NA ((uint8_t)0x00)
#define | LSM6DS3_XG_FIFO_ODR_10HZ ((uint8_t)0x08)
#define | LSM6DS3_XG_FIFO_ODR_25HZ ((uint8_t)0x10)
#define | LSM6DS3_XG_FIFO_ODR_50HZ ((uint8_t)0x18)
#define | LSM6DS3_XG_FIFO_ODR_100HZ ((uint8_t)0x20)
#define | LSM6DS3_XG_FIFO_ODR_200HZ ((uint8_t)0x28)
#define | LSM6DS3_XG_FIFO_ODR_400HZ ((uint8_t)0x30)
#define | LSM6DS3_XG_FIFO_ODR_800HZ ((uint8_t)0x38)
#define | LSM6DS3_XG_FIFO_ODR_1600HZ ((uint8_t)0x40)
#define | LSM6DS3_XG_FIFO_ODR_3300HZ ((uint8_t)0x48)
#define | LSM6DS3_XG_FIFO_ODR_6600HZ ((uint8_t)0x50)
#define | LSM6DS3_XG_FIFO_ODR_MASK ((uint8_t)0x78)
#define | LSM6DS3_XG_FIFO_MODE_BYPASS ((uint8_t)0x00)
#define | LSM6DS3_XG_FIFO_MODE_FIFO ((uint8_t)0x01)
#define | LSM6DS3_XG_FIFO_MODE_CONTINUOUS_THEN_FIFO ((uint8_t)0x03)
#define | LSM6DS3_XG_FIFO_MODE_BYPASS_THEN_CONTINUOUS ((uint8_t)0x04)
#define | LSM6DS3_XG_FIFO_MODE_CONTINUOUS_OVERWRITE ((uint8_t)0x05)
#define | LSM6DS3_XG_FIFO_MODE_MASK ((uint8_t)0x07)
#define | LSM6DS3_G_ODR_PD ((uint8_t)0x00)
#define | LSM6DS3_G_ODR_13HZ ((uint8_t)0x10)
#define | LSM6DS3_G_ODR_26HZ ((uint8_t)0x20)
#define | LSM6DS3_G_ODR_52HZ ((uint8_t)0x30)
#define | LSM6DS3_G_ODR_104HZ ((uint8_t)0x40)
#define | LSM6DS3_G_ODR_208HZ ((uint8_t)0x50)
#define | LSM6DS3_G_ODR_416HZ ((uint8_t)0x60)
#define | LSM6DS3_G_ODR_833HZ ((uint8_t)0x70)
#define | LSM6DS3_G_ODR_1660HZ ((uint8_t)0x80)
#define | LSM6DS3_G_ODR_MASK ((uint8_t)0xF0)
#define | LSM6DS3_G_FS_125_DISABLE ((uint8_t)0x00)
#define | LSM6DS3_G_FS_125_ENABLE ((uint8_t)0x02)
#define | LSM6DS3_G_FS_125_MASK ((uint8_t)0x02)
#define | LSM6DS3_G_FS_245 ((uint8_t)0x00)
#define | LSM6DS3_G_FS_500 ((uint8_t)0x04)
#define | LSM6DS3_G_FS_1000 ((uint8_t)0x08)
#define | LSM6DS3_G_FS_2000 ((uint8_t)0x0C)
#define | LSM6DS3_G_FS_MASK ((uint8_t)0x0C)
#define | LSM6DS3_G_ZEN_DISABLE ((uint8_t)0x00)
#define | LSM6DS3_G_ZEN_ENABLE ((uint8_t)0x20)
#define | LSM6DS3_G_ZEN_MASK ((uint8_t)0x20)
#define | LSM6DS3_G_YEN_DISABLE ((uint8_t)0x00)
#define | LSM6DS3_G_YEN_ENABLE ((uint8_t)0x10)
#define | LSM6DS3_G_YEN_MASK ((uint8_t)0x10)
#define | LSM6DS3_G_XEN_DISABLE ((uint8_t)0x00)
#define | LSM6DS3_G_XEN_ENABLE ((uint8_t)0x08)
#define | LSM6DS3_G_XEN_MASK ((uint8_t)0x08)
#define | LSM6DS3_XL_ODR_PD ((uint8_t)0x00)
#define | LSM6DS3_XL_ODR_13HZ ((uint8_t)0x10)
#define | LSM6DS3_XL_ODR_26HZ ((uint8_t)0x20)
#define | LSM6DS3_XL_ODR_52HZ ((uint8_t)0x30)
#define | LSM6DS3_XL_ODR_104HZ ((uint8_t)0x40)
#define | LSM6DS3_XL_ODR_208HZ ((uint8_t)0x50)
#define | LSM6DS3_XL_ODR_416HZ ((uint8_t)0x60)
#define | LSM6DS3_XL_ODR_833HZ ((uint8_t)0x70)
#define | LSM6DS3_XL_ODR_1660HZ ((uint8_t)0x80)
#define | LSM6DS3_XL_ODR_3330HZ ((uint8_t)0x90)
#define | LSM6DS3_XL_ODR_6660HZ ((uint8_t)0xA0)
#define | LSM6DS3_XL_ODR_MASK ((uint8_t)0xF0)
#define | LSM6DS3_XL_FS_2G ((uint8_t)0x00)
#define | LSM6DS3_XL_FS_4G ((uint8_t)0x08)
#define | LSM6DS3_XL_FS_8G ((uint8_t)0x0C)
#define | LSM6DS3_XL_FS_16G ((uint8_t)0x04)
#define | LSM6DS3_XL_FS_MASK ((uint8_t)0x0C)
#define | LSM6DS3_XL_BW_400HZ ((uint8_t)0x00)
#define | LSM6DS3_XL_BW_200HZ ((uint8_t)0x01)
#define | LSM6DS3_XL_BW_100HZ ((uint8_t)0x02)
#define | LSM6DS3_XL_BW_50HZ ((uint8_t)0x03)
#define | LSM6DS3_XL_BW_MASK ((uint8_t)0x03)
#define | LSM6DS3_XL_ZEN_DISABLE ((uint8_t)0x00)
#define | LSM6DS3_XL_ZEN_ENABLE ((uint8_t)0x20)
#define | LSM6DS3_XL_ZEN_MASK ((uint8_t)0x20)
#define | LSM6DS3_XL_YEN_DISABLE ((uint8_t)0x00)
#define | LSM6DS3_XL_YEN_ENABLE ((uint8_t)0x10)
#define | LSM6DS3_XL_YEN_MASK ((uint8_t)0x10)
#define | LSM6DS3_XL_XEN_DISABLE ((uint8_t)0x00)
#define | LSM6DS3_XL_XEN_ENABLE ((uint8_t)0x08)
#define | LSM6DS3_XL_XEN_MASK ((uint8_t)0x08)
#define | LSM6DS3_XG_WAKE_UP_DUR_FF_DUR5_DEFAULT ((uint8_t)0x00)
#define | LSM6DS3_XG_WAKE_UP_DUR_FF_DUR5_MASK ((uint8_t)0x80)
#define | LSM6DS3_XG_WAKE_UP_DUR_WAKE_DUR_DEFAULT ((uint8_t)0x00)
#define | LSM6DS3_XG_WAKE_UP_DUR_WAKE_DUR_MASK ((uint8_t)0x60)
#define | LSM6DS3_XG_WAKE_UP_DUR_TIMER_HR_DEFAULT ((uint8_t)0x00)
#define | LSM6DS3_XG_WAKE_UP_DUR_TIMER_HR_MASK ((uint8_t)0x10)
#define | LSM6DS3_XG_WAKE_UP_DUR_SLEEP_DUR_DEFAULT ((uint8_t)0x00)
#define | LSM6DS3_XG_WAKE_UP_DUR_SLEEP_DUR_MASK ((uint8_t)0x0F)
#define | LSM6DS3_XG_WAKE_FREE_FALL_FF_DUR_DEFAULT ((uint8_t)0x00)
#define | LSM6DS3_XG_WAKE_FREE_FALL_FF_DUR_TYPICAL ((uint8_t)0x30)
#define | LSM6DS3_XG_WAKE_FREE_FALL_FF_DUR_MASK ((uint8_t)0xF8)
#define | LSM6DS3_XG_WAKE_FREE_FALL_FF_THS_156MG ((uint8_t)0x00)
#define | LSM6DS3_XG_WAKE_FREE_FALL_FF_THS_219MG ((uint8_t)0x01)
#define | LSM6DS3_XG_WAKE_FREE_FALL_FF_THS_250MG ((uint8_t)0x02)
#define | LSM6DS3_XG_WAKE_FREE_FALL_FF_THS_312MG ((uint8_t)0x03)
#define | LSM6DS3_XG_WAKE_FREE_FALL_FF_THS_344MG ((uint8_t)0x04)
#define | LSM6DS3_XG_WAKE_FREE_FALL_FF_THS_406MG ((uint8_t)0x05)
#define | LSM6DS3_XG_WAKE_FREE_FALL_FF_THS_469MG ((uint8_t)0x06)
#define | LSM6DS3_XG_WAKE_FREE_FALL_FF_THS_500MG ((uint8_t)0x07)
#define | LSM6DS3_XG_WAKE_FREE_FALL_FF_THS_MASK ((uint8_t)0x07)
#define | LSM6DS3_XG_MD1_CFG_INT1_INACT_STATE_DISABLE ((uint8_t)0x00)
#define | LSM6DS3_XG_MD1_CFG_INT1_INACT_STATE_ENABLE ((uint8_t)0x80)
#define | LSM6DS3_XG_MD1_CFG_INT1_INACT_STATE_MASK ((uint8_t)0x80)
#define | LSM6DS3_XG_MD1_CFG_INT1_SINGLE_TAP_DISABLE ((uint8_t)0x00)
#define | LSM6DS3_XG_MD1_CFG_INT1_SINGLE_TAP_ENABLE ((uint8_t)0x40)
#define | LSM6DS3_XG_MD1_CFG_INT1_SINGLE_TAP_MASK ((uint8_t)0x40)
#define | LSM6DS3_XG_MD1_CFG_INT1_WU_DISABLE ((uint8_t)0x00)
#define | LSM6DS3_XG_MD1_CFG_INT1_WU_ENABLE ((uint8_t)0x20)
#define | LSM6DS3_XG_MD1_CFG_INT1_WU_MASK ((uint8_t)0x20)
#define | LSM6DS3_XG_MD1_CFG_INT1_FF_DISABLE ((uint8_t)0x00)
#define | LSM6DS3_XG_MD1_CFG_INT1_FF_ENABLE ((uint8_t)0x10)
#define | LSM6DS3_XG_MD1_CFG_INT1_FF_MASK ((uint8_t)0x10)
#define | LSM6DS3_XG_MD1_CFG_INT1_DOUBLE_TAP_DISABLE ((uint8_t)0x00)
#define | LSM6DS3_XG_MD1_CFG_INT1_DOUBLE_TAP_ENABLE ((uint8_t)0x08)
#define | LSM6DS3_XG_MD1_CFG_INT1_DOUBLE_TAP_MASK ((uint8_t)0x08)
#define | LSM6DS3_XG_MD1_CFG_INT1_6D_DISABLE ((uint8_t)0x00)
#define | LSM6DS3_XG_MD1_CFG_INT1_6D_ENABLE ((uint8_t)0x04)
#define | LSM6DS3_XG_MD1_CFG_INT1_6D_MASK ((uint8_t)0x04)
#define | LSM6DS3_XG_MD1_CFG_INT1_TILT_DISABLE ((uint8_t)0x00)
#define | LSM6DS3_XG_MD1_CFG_INT1_TILT_ENABLE ((uint8_t)0x02)
#define | LSM6DS3_XG_MD1_CFG_INT1_TILT_MASK ((uint8_t)0x02)
#define | LSM6DS3_XG_MD1_CFG_INT1_TIMER_DISABLE ((uint8_t)0x00)
#define | LSM6DS3_XG_MD1_CFG_INT1_TIMER_ENABLE ((uint8_t)0x01)
#define | LSM6DS3_XG_MD1_CFG_INT1_TIMER_MASK ((uint8_t)0x01)
#define | LSM6DS3_XG_WAKE_UP_SRC_FF_IA_DISABLE ((uint8_t)0x00)
#define | LSM6DS3_XG_WAKE_UP_SRC_FF_IA_ENABLE ((uint8_t)0x20)
#define | LSM6DS3_XG_WAKE_UP_SRC_FF_IA_MASK ((uint8_t)0x20)
#define | LSM6DS3_XG_WAKE_UP_SRC_SLEEP_STATE_IA_DISABLE ((uint8_t)0x00)
#define | LSM6DS3_XG_WAKE_UP_SRC_SLEEP_STATE_IA_ENABLE ((uint8_t)0x10)
#define | LSM6DS3_XG_WAKE_UP_SRC_SLEEP_STATE_IA_MASK ((uint8_t)0x10)
#define | LSM6DS3_XG_WAKE_UP_SRC_WU_IA_DISABLE ((uint8_t)0x00)
#define | LSM6DS3_XG_WAKE_UP_SRC_WU_IA_ENABLE ((uint8_t)0x08)
#define | LSM6DS3_XG_WAKE_UP_SRC_WU_IA_MASK ((uint8_t)0x08)
#define | LSM6DS3_XG_WAKE_UP_SRC_X_WU_DISABLE ((uint8_t)0x00)
#define | LSM6DS3_XG_WAKE_UP_SRC_X_WU_ENABLE ((uint8_t)0x04)
#define | LSM6DS3_XG_WAKE_UP_SRC_X_WU_MASK ((uint8_t)0x04)
#define | LSM6DS3_XG_WAKE_UP_SRC_Y_WU_DISABLE ((uint8_t)0x00)
#define | LSM6DS3_XG_WAKE_UP_SRC_Y_WU_ENABLE ((uint8_t)0x02)
#define | LSM6DS3_XG_WAKE_UP_SRC_Y_WU_MASK ((uint8_t)0x02)
#define | LSM6DS3_XG_WAKE_UP_SRC_Z_WU_DISABLE ((uint8_t)0x00)
#define | LSM6DS3_XG_WAKE_UP_SRC_Z_WU_ENABLE ((uint8_t)0x01)
#define | LSM6DS3_XG_WAKE_UP_SRC_Z_WU_MASK ((uint8_t)0x01)

## Enumerations

enum | IMU_6AXES_StatusTypeDef { IMU_6AXES_OK = 0, IMU_6AXES_ERROR = 1, IMU_6AXES_TIMEOUT = 2, IMU_6AXES_NOT_IMPLEMENTED = 3 }
| IMU_6AXES status enumerator definition. More...

## Functions

IMU_6AXES_StatusTypeDef | LSM6DS3_IO_Init (void)
IMU_6AXES_StatusTypeDef | LSM6DS3_IO_Write (uint8_t *pBuffer, uint8_t DeviceAddr, uint8_t RegisterAddr, uint16_t NumByteToWrite)
IMU_6AXES_StatusTypeDef | LSM6DS3_IO_Read (uint8_t *pBuffer, uint8_t DeviceAddr, uint8_t RegisterAddr, uint16_t NumByteToRead)
void | LSM6DS3_IO_ITConfig (void)

## Variables

IMU_6AXES_DrvTypeDef | LSM6DS3Drv
LSM6DS3_DrvExtTypeDef | LSM6DS3Drv_ext_internal

## Detailed Description

This file contains definitions for the lsm6ds3.c firmware driver.

Author
  MEMS Application Team

Version
  V1.2.0

Date
  28-May-2015

Attention

##
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Definition in file lsm6ds3.h.