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BlueNRG1_dma.h
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1
23 /* Define to prevent recursive inclusion -------------------------------------*/
24 #ifndef BLUENRG1_DMA_H
25 #define BLUENRG1_DMA_H
26
27 #ifdef __cplusplus
28 extern "C" {
29 #endif
30
31 /* Includes ------------------------------------------------------------------*/
32 #include "BlueNRG1.h"
33
49 typedef struct
50 {
51 uint32_t DMA_PeripheralBaseAddr;
53 uint32_t DMA_MemoryBaseAddr;
55 uint32_t DMA_DIR;
58 uint32_t DMA_BufferSize;
62 uint32_t DMA_PeripheralInc;
65 uint32_t DMA_MemoryInc;
68 uint32_t DMA_PeripheralDataSize;
71 uint32_t DMA_MemoryDataSize;
74 uint32_t DMA_Mode;
79 uint32_t DMA_Priority;
82 uint32_t DMA_M2M;
84 }DMA_InitType;
85
99 #define DMA_DIR_PeripheralDST ((uint32_t)0x00000010)
100 #define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)
101 #define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \
102 ((DIR) == DMA_DIR_PeripheralSRC))
103
111 #define DMA_PeripheralInc_Enable ((uint32_t)0x00000040)
112 #define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
113 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \
114 ((STATE) == DMA_PeripheralInc_Disable))
115
123 #define DMA_MemoryInc_Enable ((uint32_t)0x00000080)
124 #define DMA_MemoryInc_Disable ((uint32_t)0x00000000)
125 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \
126 ((STATE) == DMA_MemoryInc_Disable))
127
135 #define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
136 #define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100)
137 #define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200)
138 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
139 ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
140 ((SIZE) == DMA_PeripheralDataSize_Word))
141
149 #define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
150 #define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400)
151 #define DMA_MemoryDataSize_Word ((uint32_t)0x00000800)
152 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
153 ((SIZE) == DMA_MemoryDataSize_HalfWord) || \
154 ((SIZE) == DMA_MemoryDataSize_Word))
155
163 #define DMA_Mode_Circular ((uint32_t)0x00000020)
164 #define DMA_Mode_Normal ((uint32_t)0x00000000)
165 #define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal))
166
174 #define DMA_Priority_VeryHigh ((uint32_t)0x00003000)
175 #define DMA_Priority_High ((uint32_t)0x00002000)
176 #define DMA_Priority_Medium ((uint32_t)0x00001000)
177 #define DMA_Priority_Low ((uint32_t)0x00000000)
178 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \
179 ((PRIORITY) == DMA_Priority_High) || \
180 ((PRIORITY) == DMA_Priority_Medium) || \
181 ((PRIORITY) == DMA_Priority_Low))
182
190 #define DMA_M2M_Enable ((uint32_t)0x00004000)
191 #define DMA_M2M_Disable ((uint32_t)0x00000000)
192 #define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable))
193
202 #define DMA_FLAG_TC ((uint32_t)0x00000002)
203 #define DMA_FLAG_HT ((uint32_t)0x00000004)
204 #define DMA_FLAG_TE ((uint32_t)0x00000008)
205 #define IS_DMA_CONFIG_FLAG(FLAG) ((FLAG & 0x0E) != 0)
206
216 #define DMA_FLAG_GL0 ((uint32_t)0x00000001)
217 #define DMA_FLAG_TC0 ((uint32_t)0x00000002)
218 #define DMA_FLAG_HT0 ((uint32_t)0x00000004)
219 #define DMA_FLAG_TE0 ((uint32_t)0x00000008)
220 #define DMA_FLAG_GL1 ((uint32_t)0x00000010)
221 #define DMA_FLAG_TC1 ((uint32_t)0x00000020)
222 #define DMA_FLAG_HT1 ((uint32_t)0x00000040)
223 #define DMA_FLAG_TE1 ((uint32_t)0x00000080)
224 #define DMA_FLAG_GL2 ((uint32_t)0x00000100)
225 #define DMA_FLAG_TC2 ((uint32_t)0x00000200)
226 #define DMA_FLAG_HT2 ((uint32_t)0x00000400)
227 #define DMA_FLAG_TE2 ((uint32_t)0x00000800)
228 #define DMA_FLAG_GL3 ((uint32_t)0x00001000)
229 #define DMA_FLAG_TC3 ((uint32_t)0x00002000)
230 #define DMA_FLAG_HT3 ((uint32_t)0x00004000)
231 #define DMA_FLAG_TE3 ((uint32_t)0x00008000)
232 #define DMA_FLAG_GL4 ((uint32_t)0x00010000)
233 #define DMA_FLAG_TC4 ((uint32_t)0x00020000)
234 #define DMA_FLAG_HT4 ((uint32_t)0x00040000)
235 #define DMA_FLAG_TE4 ((uint32_t)0x00080000)
236 #define DMA_FLAG_GL5 ((uint32_t)0x00100000)
237 #define DMA_FLAG_TC5 ((uint32_t)0x00200000)
238 #define DMA_FLAG_HT5 ((uint32_t)0x00400000)
239 #define DMA_FLAG_TE5 ((uint32_t)0x00800000)
240 #define DMA_FLAG_GL6 ((uint32_t)0x01000000)
241 #define DMA_FLAG_TC6 ((uint32_t)0x02000000)
242 #define DMA_FLAG_HT6 ((uint32_t)0x04000000)
243 #define DMA_FLAG_TE6 ((uint32_t)0x08000000)
244 #define DMA_FLAG_GL7 ((uint32_t)0x10000000)
245 #define DMA_FLAG_TC7 ((uint32_t)0x20000000)
246 #define DMA_FLAG_HT7 ((uint32_t)0x40000000)
247 #define DMA_FLAG_TE7 ((uint32_t)0x80000000)
248
249
250 #define IS_DMA_CH_FLAG(FLAG) ((FLAG) != 0x00)
251
252
253
264 #define DMA_ADC_CHANNEL0 ((uint8_t)0x01)
265 #define DMA_ADC_CHANNEL1 ((uint8_t)0x02)
266 #define DMA_ADC_CHANNEL2 ((uint8_t)0x04)
267 #define DMA_ADC_CHANNEL3 ((uint8_t)0x08)
268 #define DMA_ADC_CHANNEL4 ((uint8_t)0x10)
269 #define DMA_ADC_CHANNEL5 ((uint8_t)0x20)
270 #define DMA_ADC_CHANNEL6 ((uint8_t)0x40)
271 #define DMA_ADC_CHANNEL7 ((uint8_t)0x80)
272
273
274 #define IS_DMA_ADC_CH(SEL) (((SEL) == DMA_ADC_CHANNEL0) || \
275 ((SEL) == DMA_ADC_CHANNEL1) || \
276 ((SEL) == DMA_ADC_CHANNEL2) || \
277 ((SEL) == DMA_ADC_CHANNEL3) || \
278 ((SEL) == DMA_ADC_CHANNEL4) || \
279 ((SEL) == DMA_ADC_CHANNEL5) || \
280 ((SEL) == DMA_ADC_CHANNEL6) || \
281 ((SEL) == DMA_ADC_CHANNEL7))
282
283
284
295 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
296
310 /* Function used to set the DMA configuration to the default reset state *****/
311 void DMA_DeInit(DMA_CH_Type* DMAy_Channelx);
312
313 /* Initialization and Configuration functions *********************************/
314 void DMA_Init(DMA_CH_Type* DMAy_Channelx, DMA_InitType* DMA_InitStruct);
315 void DMA_StructInit(DMA_InitType* DMA_InitStruct);
316 void DMA_Cmd(DMA_CH_Type* DMAy_Channelx, FunctionalState NewState);
317 void DMA_SelectAdcChannel(uint8_t DMA_AdcChannel, FunctionalState NewState);
318
319 /* Data Counter functions *****************************************************/
320 void DMA_SetCurrDataCounter(DMA_CH_Type* DMAy_Channelx, uint16_t DataNumber);
321 uint16_t DMA_GetCurrDataCounter(DMA_CH_Type* DMAy_Channelx);
322
323 /* Interrupts and flags management functions **********************************/
324 FlagStatus DMA_GetFlagStatus(uint32_t DMA_Flag);
325 void DMA_FlagConfig(DMA_CH_Type* DMAy_Channelx, uint32_t DMA_Flag, FunctionalState NewState);
326 void DMA_ClearFlag(uint32_t DMA_Flag);
327
328
342 #ifdef __cplusplus
343 }
344 #endif
345
346 #endif /*BLUENRG1_DMA_H */
347
348 /******************* (C) COPYRIGHT 2016 STMicroelectronics *****END OF FILE****/
DMA_Cmd
void DMA_Cmd(DMA_CH_Type *DMAy_Channelx, FunctionalState NewState)
Enables or disables the specified DMAy Channelx.
Definition: BlueNRG1_dma.c:274
DMA_FlagConfig
void DMA_FlagConfig(DMA_CH_Type *DMAy_Channelx, uint32_t DMA_Flag, FunctionalState NewState)
Enables or disables the specified DMAy Channelx interrupts.
Definition: BlueNRG1_dma.c:364
DMA_SelectAdcChannel
void DMA_SelectAdcChannel(uint8_t DMA_AdcChannel, FunctionalState NewState)
Enables or disables the specified DMA ADC Channel.
Definition: BlueNRG1_dma.c:298
DMA_InitType::DMA_PeripheralInc
uint32_t DMA_PeripheralInc
Definition: BlueNRG1_dma.h:62
DMA_InitType::DMA_PeripheralDataSize
uint32_t DMA_PeripheralDataSize
Definition: BlueNRG1_dma.h:68
DMA_SetCurrDataCounter
void DMA_SetCurrDataCounter(DMA_CH_Type *DMAy_Channelx, uint16_t DataNumber)
Sets the number of data units in the current DMAy Channelx transfer.
Definition: BlueNRG1_dma.c:324
DMA_InitType::DMA_Mode
uint32_t DMA_Mode
Definition: BlueNRG1_dma.h:74
DMA_InitType::DMA_Priority
uint32_t DMA_Priority
Definition: BlueNRG1_dma.h:79
DMA_InitType::DMA_M2M
uint32_t DMA_M2M
Definition: BlueNRG1_dma.h:82
DMA_InitType::DMA_DIR
uint32_t DMA_DIR
Definition: BlueNRG1_dma.h:55
DMA_DeInit
void DMA_DeInit(DMA_CH_Type *DMAy_Channelx)
Deinitializes the DMAy Channelx registers to their default reset values.
Definition: BlueNRG1_dma.c:116
DMA_StructInit
void DMA_StructInit(DMA_InitType *DMA_InitStruct)
Fills each DMA_InitStruct member with its default value.
Definition: BlueNRG1_dma.c:239
DMA_InitType::DMA_PeripheralBaseAddr
uint32_t DMA_PeripheralBaseAddr
Definition: BlueNRG1_dma.h:51
DMA_ClearFlag
void DMA_ClearFlag(uint32_t DMA_Flag)
Clears the DMAy Channelx's pending flags.
Definition: BlueNRG1_dma.c:487
DMA_InitType::DMA_BufferSize
uint32_t DMA_BufferSize
Definition: BlueNRG1_dma.h:58
DMA_InitType
DMA Init structure definition.
Definition: BlueNRG1_dma.h:49
DMA_Init
void DMA_Init(DMA_CH_Type *DMAy_Channelx, DMA_InitType *DMA_InitStruct)
Initializes the DMAy Channelx according to the specified parameters in the DMA_InitStruct.
Definition: BlueNRG1_dma.c:182
DMA_InitType::DMA_MemoryDataSize
uint32_t DMA_MemoryDataSize
Definition: BlueNRG1_dma.h:71
DMA_GetCurrDataCounter
uint16_t DMA_GetCurrDataCounter(DMA_CH_Type *DMAy_Channelx)
Returns the number of remaining data units in the current DMAy Channelx transfer. ...
Definition: BlueNRG1_dma.c:342
DMA_GetFlagStatus
FlagStatus DMA_GetFlagStatus(uint32_t DMA_Flag)
Checks whether the specified DMAy Channelx flag is set or not.
Definition: BlueNRG1_dma.c:422
DMA_InitType::DMA_MemoryBaseAddr
uint32_t DMA_MemoryBaseAddr
Definition: BlueNRG1_dma.h:53
DMA_InitType::DMA_MemoryInc
uint32_t DMA_MemoryInc
Definition: BlueNRG1_dma.h:65